SOI Lateral DMOSFET with Graded Doping and Shallow Trench Insulator
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Solution Overview
Problem
In high voltage power MOSFETs, there is a trade-off between maximizing breakdown voltage (BVDSS) and minimizing on-resistance (RDSON), with conventional designs facing challenges in optimizing these parameters while minimizing electric field effects, parasitic capacitance, and improving switching frequencies.
Innovation Solution
A semiconductor device with a substrate and buried oxide layer, featuring a graded doping distribution in the LDD drift region, a co-implant region, and a shallow trench insulator along the LDD drift region, which reduces RDSON and enhances BVDSS by allowing a higher electric field to be sustained within the insulator, thereby optimizing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker or lightly doped drift region is provided to increase breakdown voltage, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a graded doping distribution in the drift region where the doping concentration varies spatially - lighter doping near the drain for high breakdown voltage and heavier doping near the source for lower on-resistance. This non-uniform doping profile optimizes both contradictory parameters locally rather than using a uniform doping concentration throughout the drift region.
Solution Approach 2:
The patent changes the doping concentration parameter along the drift region length, transitioning from a constant doping parameter to a variable doping parameter that gradients from the drain to source. This parameter change enables the drift region to simultaneously achieve high breakdown voltage capability and acceptable on-resistance by adjusting the effective doping level at different positions.
2Reliability
If a lower doping concentration in LDD1 is used to reduce electric field, then electric field is reduced, but on-resistance increases
Solution Approach 1:
The patent applies local quality by differentiating the doping concentrations in LDD1 and LDD2 regions, with LDD1 having lower doping for electric field control near the gate and LDD2 having higher doping for reduced on-resistance near the drain. This spatial differentiation of doping quality resolves the contradiction between electric field management and resistance reduction.
Solution Approach 2:
The patent segments the drift region into multiple laterally diffused drain (LDD) regions with different doping concentrations - LDD1 adjacent to the gate and LDD2 adjacent to the drain. This segmentation allows each segment to be optimized for its specific function: LDD1 for electric field control and LDD2 for conduction, thereby resolving the contradiction.
3Ease of manufacture
If conventional LDMOS structure is used, then manufacturing is simplified, but breakdown voltage and on-resistance optimization is limited
Solution Approach 1:
The patent maintains the conventional LDMOS manufacturing simplicity while improving performance by introducing local quality variations through graded doping in the drift region and selective LDD region doping. This approach enhances breakdown voltage and on-resistance characteristics without fundamentally changing the manufacturing process complexity.
Solution Approach 2:
The patent creates a composite doping structure within the drift region, combining multiple doping zones (LDD1 with lower concentration, LDD2 with higher concentration, and the main drift region with graded doping) to achieve superior electrical characteristics while maintaining compatibility with conventional LDMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a high breakdown voltage exceeding 150 VDC with reduced on-resistance below 100 milliohms, enabling higher switching frequencies and miniaturization of power supply components without increased reverse-recovery switching losses.
Implementation Method 1
allowing a higher electric field to be sustained within the insulator
Implementation Method 2
Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device
Data Source
AI summary
A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator.