Silicon-on-Insulator Layer Stack for Flatness and Surface Roughness
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Solution Overview
Problem
Existing methods for preparing silicon-on-insulator (SOI) struggle with achieving uniform thickness and surface roughness, particularly due to the limitations of mechanical grinding and chemical-mechanical polishing, which result in a thickness deviation of 0.2 μm and surface roughness that are difficult to further reduce.
Innovation Solution
A method involving the formation of a first etching stop layer, a second etching stop layer, and a device layer on a p-type monocrystalline silicon epitaxial substrate, followed by selective etchings using specific solutions to control thickness deviation and surface roughness, including a sacrificial oxidation treatment and thermal annealing to achieve a silicon-on-insulator film with less than 5 nm thickness deviation and 4 Å surface roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mechanical grinding and chemical-mechanical polishing are used to control thickness deviation, then the thickness uniformity is improved to about 0.2 μm, but the surface roughness cannot be reduced further and the complexity of the process increases
Solution Approach 1:
The patent divides the single thick etching stop layer into two thinner layers (first etching stop layer and second etching stop layer), each with different materials and etching selectivities. This segmentation allows independent optimization of each layer's thickness control, achieving better overall uniformity without requiring excessive mechanical processing complexity.
Solution Approach 2:
The patent changes the material parameter of the etching stop layers by using different materials (intrinsic silicon for the first layer, germanium-silicon alloy for the second layer) with different etching selectivities. This allows precise control of thickness deviation through chemical etching processes rather than relying solely on mechanical grinding and polishing.
2Manufacturing precision
If the thickness deviation of the etching stop layer is reduced to meet flattened silicon-on-insulator requirements, then the quality of SOI substrate is improved, but the difficulty of decreasing the thickness deviation increases significantly
Solution Approach 1:
The patent applies different material compositions and etching selectivities to different local regions (layers) of the etching stop structure. The first etching stop layer uses intrinsic silicon with specific etching characteristics, while the second layer uses germanium-silicon alloy with different etching properties. This local differentiation enables precise thickness control in each layer without requiring extreme reduction of overall thickness deviation through difficult mechanical processes.
Solution Approach 2:
The patent replaces reliance on mechanical grinding and polishing with a chemical etching system using selectively etched layers. By using etching solutions that selectively remove materials at different rates based on composition, the patent achieves precise thickness control through chemical processes rather than mechanical removal, significantly easing the manufacturing difficulty.
3Manufacturing precision
If multiple etching steps with different solutions are used to remove different layers, then the thickness uniformity and surface smoothness are improved to less than 5 nm and 4 Å respectively, but the number of process steps increases
Solution Approach 1:
The patent segments the etching process into three distinct steps, each targeting a specific layer with a specifically designed etching solution. This segmentation allows each etching step to be optimized for its specific target, achieving superior thickness uniformity and surface smoothness control that would be difficult to achieve in a single etching step.
Solution Approach 2:
The patent changes the chemical composition parameters of the etching solutions for each step to match the specific material being etched. By tailoring the etching solution chemistry to each layer's material composition, the patent achieves high precision thickness and surface control while maintaining reasonable process efficiency through selective etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method optimizes the thickness uniformity and surface smoothness of the silicon-on-insulator film to less than 5 nm deviation and 4 Å roughness, enhancing the flatness and quality of the SOI substrate.
Implementation Method 1
performing a first etching by using a first etching solution to remove a remaining epitaxial substrate
Implementation Method 2
performing a second etching by using a second etching solution to remove the first etching stop layer
Implementation Method 3
performing a third etching by using a third etching solution to remove the second etching stop layer and forming a silicon-on-insulator structure
Implementation Method 4
subjecting the silicon-on-insulator structure to a sacrificial oxidation treatment to remove a part of the device layer
Implementation Method 5
performing a thermal treatment to obtain a silicon-on-insulator film
Data Source
AI summary
In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 Å, respectively, so as to realize the flatness of the silicon-on-insulator film.