SOI Substrate Layer Transfer Using Voids for Controlled Cleaving
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Solution Overview
Problem
Existing methods for forming semiconductor-on-insulator (SOI) substrates face challenges in controlling the splitting of porous silicon layers, leading to rough surfaces, increased operation complexity, and potential damage to device layers, resulting in lower productivity and higher costs.
Innovation Solution
A silicon germanium (SiGe) enhanced layer-transfer (SELAT) approach is introduced, utilizing voids as break-away holes to confine the cleaving direction and reduce surface roughness, enabling efficient separation of device layers and improving recycling rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to split porous silicon layers, then separation of device layers is achieved, but surface roughness increases and operation complexity increases
Solution Approach 1:
The patent introduces voids as break-away holes that segment the multilayer structure into controlled regions. These voids act as predetermined separation planes that guide the cleaving process, allowing the structure to be divided into manageable segments with smooth surfaces rather than creating rough, uncontrolled fracture surfaces.
Solution Approach 2:
The voids are formed in advance before the cleaving operation. By pre-creating these break-away holes at specific locations, the patent prepares the structure for controlled separation, eliminating the need for complex real-time control during the splitting process and reducing operational complexity.
2Reliability
If conventional splitting methods are used, then device layers are separated, but potential damage to device layers occurs
Solution Approach 1:
The voids serve as intermediary break-away features that mediate the separation process. Instead of directly fracturing through the device layers, the cleaving process utilizes these pre-formed voids as intermediate separation zones, allowing stress to be concentrated in controlled locations away from the device layers and preventing damage while maintaining efficient separation.
3Manufacturing precision
If porous silicon layers are split without controlled cleaving, then separation is achieved, but surface roughness increases
Solution Approach 1:
The patent applies local quality by creating voids at specific strategic locations within the multilayer structure. These localized break-away holes provide controlled initiation points for cleaving, ensuring that the separation occurs at predetermined positions with smooth surfaces rather than creating rough, uncontrolled fracture surfaces across the entire structure.
4Productivity
If unnecessary layers are removed using conventional methods, then device layer is exposed, but operation complexity and time increase
Solution Approach 1:
The patent extracts or removes the sacrificial layer that contains the voids after it has served its purpose as a cleaving template. This extraction approach allows the device layer to be exposed and the sacrificial material to be discarded in a single efficient operation, rather than requiring multiple sequential steps to remove different layers, thereby reducing both operation complexity and time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances productivity and reduces operation costs by simplifying the removal of unnecessary layers and increasing the recycling rate of substrates, while maintaining the quality of the device layer for subsequent semiconductor manufacturing.
Implementation Method 1
An epitaxial growth operation is performed to seal the trenches with a first semiconductor material, and a plurality of voids are formed in the first multilayered structure
Data Source
AI summary
A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.