SOI Substrate Layer Stack for Controlled Wafer Splitting
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Solution Overview
Problem
The complexity of semiconductor processing and manufacturing increases with the scaling down of integrated circuits, necessitating advancements in forming semiconductor-on-insulator (SOI) substrates to improve efficiency and reduce costs.
Innovation Solution
A method involving the formation of multiple semiconductor layers with controlled implantation of hydrogen ions, followed by bonding and wafer splitting to create a semiconductor-on-insulator (SOI) substrate, utilizing diffusion and implant capture layers to manage implant species and facilitate efficient wafer splitting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor processing methods are used for scaling down, then manufacturing capability is maintained, but processing complexity increases and production efficiency decreases
Solution Approach 1:
The patent segments the semiconductor layer into multiple distinct layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) with different compositions and functions. This segmentation allows each layer to be optimized independently for specific purposes (e.g., stress control, electrical properties, mechanical strength), thereby simplifying the overall processing by breaking down complex monolithic structures into manageable, functionally-specialized components that can be manufactured with standard techniques.
2Productivity
If geometry size is decreased to increase functional density, then more circuits fit per chip area, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating semiconductor layers with spatially varying compositions and properties. The first, second, and third semiconductor layers have different germanium concentrations, doping levels, and crystal structures tailored to specific locations and functions within the device. This allows each region to be optimized for its specific role (e.g., high-mobility channels, stress-induced performance enhancement, mechanical support) without requiring uniform high precision across the entire structure, thereby enabling higher functional density with achievable manufacturing precision.
3Reliability
If multiple semiconductor layers with different compositions are formed, then device performance is improved, but process steps increase
Solution Approach 1:
The patent employs a nested doll structure where multiple semiconductor layers are stacked one within another in a vertical configuration. The first semiconductor layer is positioned at a first depth, the second at a second depth, and the third at a third depth, creating a vertically-integrated multi-layer structure. This nesting approach allows complex multi-material, multi-functionality device architectures to be achieved through vertical stacking rather than lateral integration, reducing the horizontal footprint and simplifying interconnect routing while maintaining high device performance through controlled composition gradients and interface engineering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the quality and efficiency of SOI wafer production by controlling implant distribution and facilitating effective wafer splitting, thereby improving the fabrication of integrated circuits.
Implementation Method 1
the first semiconductor layer may serve as a diffusion barrier layer to slow down the implantation species
Implementation Method 2
the second semiconductor layer may serve as an implant capture layer to trap the implantation species within the second semiconductor layer
Implementation Method 3
the bonded structure is split by applying stress to separate the first semiconductor layer from the substrate
Data Source
AI summary
A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer has a higher germanium concentration than the second semiconductor layer; forming a semiconductor cap over the second semiconductor layer; forming a first bonding layer over the semiconductor cap; bonding the first boding layer to a second bonding layer over a carrier substrate to form a bonded structure; and performing a wafer splitting process to split the first semiconductor layer into a first portion and a second portion separated from each other, such that the first portion of the first semiconductor layer and the substrate are removed from the bonded structure.