SOI LDMOS Structure for Smaller Area and High Breakdown Voltage
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Solution Overview
Problem
Current LDMOS devices have a large area due to the laterally diffused drain, leading to high cost and scaling challenges, which is a barrier for high-frequency wireless communication applications.
Innovation Solution
A semiconductor device structure with a semiconductor layer over an insulator layer, featuring a well, doped region, and drift region, along with a gate stack, optimized through specific doping and epitaxial growth processes to reduce the device area while maintaining high breakdown voltage and output power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laterally diffused drain structure is used in LDMOS devices, then high breakdown voltage and high output power are achieved, but the device area becomes large leading to high cost and scaling challenges
Solution Approach 1:
The patent transitions from a conventional planar lateral diffusion structure to a vertically-oriented SIMOX structure. The drain region is formed by implanting dopants through the silicon layer into the buried oxide layer, creating a vertical junction rather than a lateral one. This dimensional change allows the high-field region to be confined vertically under the gate, reducing the lateral area required while maintaining high breakdown voltage through the thick buried oxide layer.
Solution Approach 2:
The patent embeds the active drain region within the buried oxide layer, which itself is part of the SOI substrate structure. The dopant implantation creates a nested configuration where the doped region is contained within the oxide layer, which is sandwiched between the silicon device layer and the substrate. This nesting allows compact integration while maintaining the electrical isolation and high voltage characteristics.
2Power
If a laterally diffused drain structure is used in LDMOS devices, then high output power is achieved, but scaling challenges arise due to large device area
Solution Approach 1:
The patent achieves power density improvement by moving the high-voltage handling function to the vertical dimension through the buried oxide layer. The lateral area under the gate is reduced because the drain extension and high-field region are formed vertically through implantation into the oxide, rather than requiring large lateral diffusion regions. This allows higher power output from a smaller footprint device.
3Speed
If conventional LDMOS structure is used, then radio frequency performance is achieved, but cost is high due to large device area
Solution Approach 1:
The SIMOX structure maintains RF performance by preserving the essential LDMOS field distribution under the gate through vertical dopant implantation. The high-frequency characteristics are determined by the gate-drain field distribution, which is maintained through the vertical junction geometry. The reduced lateral area lowers parasitic capacitances, potentially improving RF performance while reducing cost through smaller device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces device area, lowering costs and addressing scaling challenges while maintaining high performance for radio frequency circuits, suitable for power amplifiers in wireless communication.
Implementation Method 1
A doped region is above and coupled with the well, and the doped region is in the insulator layer
Implementation Method 2
A drift region is above and coupled with the doped region, and the drift region is at least partially in the semiconductor layer
Data Source
AI summary
A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A well is in the base layer, a doped region is above and coupled with the well, and the doped region is in the insulator layer. A drift region is above and coupled with the doped region, and the drift region is at least partially in the semiconductor layer. A gate stack is partially over the semiconductor layer and partially over drift region.