SOI-LIGBT Current Density via Segmented PNP Structure
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Solution Overview
Problem
Conventional N-type Silicon-On-Insulator Lateral Insulated-Gate Bipolar Transistors (SOI-LIGBTs) have low current density, requiring increased device area for higher current driving capability, which leads to higher costs without matching improvements in voltage withstand.
Innovation Solution
A high-current N-type SOI-LIGBT design featuring a symmetric structure with multiple transistors and oxide layers, enhancing current density through amplified base current via PNP-type high-voltage bipolar transistors without increasing layout area or compromising voltage ratings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of lateral devices is increased to obtain higher current driving capability, then the current driving capability is improved, but the chip area consumption increases and cost increases
Solution Approach 1:
The device is segmented into multiple functional regions including first and second P-type body regions, first and second N-type source regions, first and second N-type base regions, and first and second P-type drain regions. This segmentation allows current to flow through multiple parallel paths, effectively increasing current driving capability without proportionally increasing chip area.
Solution Approach 2:
The patent implements a nested structure where N-type source regions are positioned within P-type body regions, which are in turn positioned within N-type buffer well regions. This nested arrangement maximizes the use of available space, allowing multiple functional layers to coexist in a compact footprint, thereby increasing current capacity without linearly increasing chip area.
2Productivity
If the area of lateral devices is increased to obtain higher current driving capability, then the current driving capability is improved, but the manufacturing cost increases
Solution Approach 1:
The device is segmented into multiple functional regions including first and second P-type body regions, first and second N-type source regions, first and second N-type base regions, and first and second P-type drain regions. This segmentation allows current to flow through multiple parallel paths, effectively increasing current driving capability without proportionally increasing chip area.
Solution Approach 2:
The patent implements a nested structure where N-type source regions are positioned within P-type body regions, which are in turn positioned within N-type buffer well regions. This nested arrangement maximizes the use of available space, allowing multiple functional layers to coexist in a compact footprint, thereby increasing current capacity without linearly increasing chip area.
Data Source
AI summary
A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.