SOI Integrated Circuits Local Oxidation STI Isolation
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Solution Overview
Problem
Silicon-on-insulator (SOI) integrated circuits face issues such as reduced threshold voltages, leakage currents, complex manufacturing processes, and increased device area due to the 'floating body' effect and parasitic capacitance, which affect the performance and efficiency of transistors.
Innovation Solution
The implementation of shallow trench isolation (STI) regions and a local oxide layer in the semiconductor substrate, along with a gate dielectric layer, to electrically isolate devices and reduce parasitic capacitance, while maintaining a simpler manufacturing process and smaller device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If body contacting method is used to connect the floating body to fixed potential, then the threshold voltage stability is improved, but the device area increases and manufacturing complexity increases
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trench isolation regions for device isolation, a local oxide layer for parasitic capacitance reduction, and a dielectric layer for electrical isolation. This segmented approach allows each component to perform its specific function efficiently without requiring complex body contacting structures, thereby maintaining threshold voltage stability while simplifying manufacturing.
Solution Approach 2:
The patent extracts and removes the need for complex body contacting methods by implementing a floating body configuration with shallow trench isolation and local oxide layers that inherently manage the floating body effects. This extraction eliminates the need for additional body contact structures, reducing manufacturing complexity while maintaining device performance.
2Object-affected harmful factors
If shallow trench isolation regions are implemented to electrically isolate devices, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple functions into the shallow trench isolation structure: it provides device isolation, reduces parasitic capacitance through the local oxide layer, and enables efficient fabrication using standard CMOS processes. By combining these functions into a unified structure formed through integrated process steps, the patent achieves parasitic capacitance reduction without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent utilizes parameter changes in the oxidation process to form the local oxide layer with specific depth and spatial distribution. By controlling oxidation parameters (temperature, time, atmosphere), the patent achieves precise control over the oxide layer properties, enabling effective parasitic capacitance reduction while maintaining compatibility with standard manufacturing processes.
3Speed
If the gate length is reduced to improve transistor performance, then switching speed increases, but feature size control difficulty increases
Solution Approach 1:
The patent implements preliminary actions through the shallow trench isolation and local oxide layer formation before transistor fabrication. These pre-formed structures establish precise geometric boundaries and electrical isolation that guide subsequent processing steps, enabling accurate feature size control even as gate lengths are reduced to improve switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, improves transistor performance by minimizing the 'floating body' effect, and allows for more efficient fabrication with fewer processes, resulting in higher integration density and reduced power consumption.
Implementation Method 1
reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors
Implementation Method 2
a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate
Implementation Method 3
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer
Implementation Method 4
oxidizing a second portion of the semiconductor substrate, thereby forming a local oxide region that extends a second depth below an upper surface of the semiconductor substrate
Data Source
AI summary
Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor that includes source and drain regions located in the semiconductor substrate, a gate dielectric layer located between the source and drain regions, and a local oxide layer located in a second portion of the semiconductor substrate and extending a second depth below the upper surface of the semiconductor substrate. The first depth is greater than the second depth. Still further, the integrated circuit includes a first gate electrode that extends over the gate dielectric layer and the local oxide layer.