Localized High Resistivity Regions in SOI Substrates
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Solution Overview
Problem
Manufacturing integrated circuits on high resistivity substrates leads to material migration during anneal processes and increased arcing risks during back end of line etching due to charge buildup, which complicates the formation of reliable RF circuits.
Innovation Solution
Creating localized regions of high resistivity in the base semiconductor layer using techniques such as patterned etching and ion implantation to form high-resistivity plugs or damaged regions, which are positioned beneath the integrated circuits to reduce material migration and arcing risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire base semiconductor layer is implanted with neutral species to form high resistivity, then RF circuit performance is improved by reducing eddy current losses, but material migration occurs during anneal processes and arcing risks increase during BEOL etching
Solution Approach 1:
The patent applies local quality by creating localized high-resistivity regions only in specific areas of the base semiconductor layer where RF circuits are positioned, rather than treating the entire substrate. This is achieved through patterned ion implantation or selective epitaxial growth of insulating layers, which introduces high resistivity (e.g., >1000 ohm-cm) only in targeted zones. This localized approach maintains the electrical benefits for RF circuits while preventing material migration and charge buildup in non-RF areas, thereby eliminating the harmful effects associated with global high-resistivity treatment.
2Loss of energy
If high resistivity is applied to the entire base semiconductor layer, then eddy current losses are reduced for RF circuits, but manufacturing complexity increases due to process complications
Solution Approach 1:
The patent reduces manufacturing complexity by applying high resistivity locally only where RF circuits are formed, using selective ion implantation or targeted epitaxial growth. This avoids the need for complex process control required for global high-resistivity treatment, while still achieving the energy loss reduction benefit in the relevant areas.
Solution Approach 2:
The patent segments the base semiconductor layer into distinct regions: high-resistivity zones underlying RF circuits and normal-resistivity areas for other circuits. This segmentation is achieved through spatially selective processing steps, allowing different resistivity characteristics in different areas without requiring complex global process control, thereby simplifying manufacturing while maintaining energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The localized high resistivity regions effectively mitigate material migration and arcing issues, enhancing the reliability and performance of RF circuits by maintaining high resistivity only where needed, thereby improving circuit stability and reducing manufacturing complexities.
Implementation Method 1
post-implanting a neutral species in the entire base semiconductor layer to form highly damaged layers with high trap density in the bandgap
Implementation Method 2
forming RF circuits over a base semiconductor layer substrate having a relatively high resistivity may reduce the eddy current losses for the RF circuit
Implementation Method 3
there is a higher chance for arcing during BEOL (back end of line) etching processes due to charge buildup when using such high resistivity substrates
Data Source
AI summary
One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.