SOI Floating-Gate Memory Cell With Bulk Silicon Channel
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Solution Overview
Problem
Non-volatile memory devices are not compatible with silicon-on-insulator (SOI) substrates due to limitations in forming source and drain regions in the thin silicon layer, which negatively impacts memory cell performance, while other devices like CMOS logic and high voltage devices benefit from SOI substrates.
Innovation Solution
A memory device is developed using a SOI substrate with a bulk silicon layer, an insulation layer, and a thin silicon layer, where source and drain regions are formed in the bulk silicon, and memory cells include a floating gate, select gate, control gate, and erase gate, with the floating gate utilizing a combination of the thin silicon layer and polysilicon or epitaxially grown silicon to increase thickness and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If source and drain regions are formed in the thin silicon layer of SOI substrate, then the device is compatible with SOI substrate structure, but the depth of source and drain regions is limited which negatively impacts memory cell performance
Solution Approach 1:
The invention divides the substrate into two distinct regions: a thin silicon layer region for forming source and drain regions, and a bulk silicon region for forming the channel. This segmentation allows source and drain regions to be formed in the thin silicon layer while the channel extends into the bulk silicon, achieving both SOI compatibility and adequate channel depth for memory cell performance
Solution Approach 2:
The invention transitions from a two-dimensional planar structure to a three-dimensional structure where the channel region extends vertically into the bulk silicon substrate. This dimensional change enables the channel to access the deeper bulk silicon region while source and drain remain in the thin silicon layer, resolving the depth limitation
2Ease of manufacture
If source and drain regions are formed in the thin silicon layer of SOI substrate, then fabrication is simplified, but the depth limitation impacts memory cell performance
Solution Approach 1:
The invention applies different structural characteristics to different locations: the thin silicon layer is maintained in regions where source and drain regions are formed, while bulk silicon is exposed in the channel region. This local differentiation allows simplified fabrication in source/drain areas while providing adequate channel depth where needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the fabrication process, enhances memory cell functionality and reliability by improving doping control and reducing programming issues related to ballistic electron transport, while allowing for the formation of both memory and logic devices on the same substrate.
Implementation Method 1
The insulation layer is typically silicon dioxide (oxide). This substrate configuration reduces parasitic device capacitance, thereby improving performance.
Implementation Method 2
The floating gate is disposed vertically over and insulated from a first portion of the channel region for directly controlling the conductivity of the first portion of the channel region
Implementation Method 3
the control gate is disposed vertically over and insulated from the floating gate for capacitive coupling therewith
Data Source
AI summary
A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.