SOI Memory Transistor Layout Using Dummy HKMG Gates Against Dishing
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Solution Overview
Problem
Existing SOI-based HKMG transistors face challenges in integrating low-voltage and high-voltage applications on the same substrate due to dishing effects during polishing processes, which affect the integrity of high-voltage transistor HKMG structures.
Innovation Solution
The implementation of a semiconductor device with both low-voltage and high-voltage transistors on a single SOI substrate, where high-voltage transistors utilize multiple HKMG structures as dummy gate structures to prevent dishing effects during polishing, allowing for concurrent formation of HKMG structures for both voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polishing processes are used for SOI substrates with high-voltage transistors, then manufacturing efficiency is maintained, but dishing effects occur that damage the HKMG structure integrity
Solution Approach 1:
The patent applies preliminary action by forming a dummy gate structure before the metal gate structure. This dummy gate structure serves as a sacrificial element that protects the actual HKMG structure during subsequent polishing processes. The dummy gate is formed in advance, allowing the real gate to be shielded from mechanical damage while maintaining manufacturing efficiency.
Solution Approach 2:
The dummy gate structure acts as an intermediary between the polishing process and the sensitive HKMG structure. It absorbs the mechanical stress and dishing effects during CMP, protecting the actual gate from damage. This intermediary element enables the polishing process to proceed without compromising gate integrity.
2Productivity
If separate processing for low-voltage and high-voltage transistors is performed, then device performance is optimized, but manufacturing time and complexity increase
Solution Approach 1:
The patent merges the processing of low-voltage and high-voltage transistors into a single concurrent process. Both transistor types are fabricated on the same substrate using the same HKMG formation steps, eliminating the need for separate processing lines. This integration significantly reduces manufacturing cycle time while maintaining device performance through the protective dummy gate mechanism.
Solution Approach 2:
The dummy gate structure serves multiple functions: it protects high-voltage transistor gates during polishing, enables concurrent processing of different voltage devices, and maintains manufacturing efficiency. This multi-functional element allows the process to handle both low-voltage and high-voltage devices without requiring separate processing sequences.
Data Source
AI summary
A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.