SOI Memory Cell Array With Shared Source-Drain Regions
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) cells with electrically floating body transistors face challenges in reducing leakage current and enhancing scaling while maintaining effective data retention and reading accuracy, particularly in semiconductor-on-insulator (SOI) devices.
Innovation Solution
The development of a memory cell array with transistors having shared source and drain regions made of different materials and crystalline structures, which reduces disturbance between adjacent memory cells during read and write operations by facilitating rapid recombination of charge carriers, and the use of specific voltage control signals for programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM cells with electrically floating body transistors are used, then data retention and reading accuracy are maintained, but leakage current increases and scaling is limited
Solution Approach 1:
The patent divides the semiconductor layer into distinct regions: a first semiconductor layer forming the body region, and a second semiconductor layer forming the source and drain regions. This segmentation allows different material compositions and crystalline structures in different regions, enabling reduced leakage current in source/drain while maintaining the floating body effect for data retention.
Solution Approach 2:
The patent applies different material properties to different regions: the body region uses one material composition while source/drain regions use another. Specifically, the source and drain regions are formed with a second semiconductor layer having different crystalline structure or composition, creating locally optimized properties that reduce leakage without affecting the overall floating body functionality.
2Productivity
If memory cell size is reduced for scaling, then device density increases, but disturbance between adjacent memory cells increases
Solution Approach 1:
The patent introduces a common doped region in the first semiconductor layer beneath the channel, with doping concentration different from the body region. This local doping modification creates an electric field configuration that confines charge carriers within the intended memory cell, preventing carrier diffusion into adjacent cells and reducing disturbance effects.
Solution Approach 2:
The patent introduces an intermediate doped region that acts as a barrier or confining structure between the channel and adjacent memory cell regions. This intermediate region with specific doping characteristics serves as a mediator that controls charge carrier movement, preventing unwanted interaction between adjacent cells while maintaining cell functionality.
3Loss of energy
If different material compositions are used in source/drain regions, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions into the source and drain regions: they serve as both the electrical contacts and the leakage reduction structures. By forming source/drain from a second semiconductor layer with different material properties, the structure achieves both electrical functionality and leakage reduction in a single integrated region, rather than requiring separate components.
Solution Approach 2:
The patent employs composite material structure with a first semiconductor layer for the body and a second semiconductor layer for source/drain regions. These layers have different material compositions or crystalline structures, creating a composite structure that leverages the advantages of each material: the body material for floating body effect and the source/drain material for reduced leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention and reading accuracy by minimizing disturbance between memory cells, allowing for more efficient programming and reading operations with reduced power consumption and improved scaling capabilities.
Implementation Method 1
shared source and drain regions made of different materials and crystalline structures, which reduces disturbance between adjacent memory cells during read and write operations by facilitating rapid recombination of charge carriers
Data Source
AI summary
An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the gate and gate dielectric are disposed on or above the first semiconductor layer that is disposed on or above an insulating layer or region, (ii) the body region of each transistor is electrically floating, (iii) the transistors of adjacent memory cells include a layout that provides a common first region, and (iv) the first regions of the transistors are comprised of a semiconductor material which is different from the material of the first semiconductor layer. Also disclosed are inventive methods of manufacturing, for example, such integrated circuit devices.