SOI Memory Structure With Split Silicon Thickness for Compact DRAM
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Solution Overview
Problem
Existing semiconductor device manufacturing techniques face challenges in reducing the size of dynamic random access memory (DRAM) devices due to aspect ratio issues and layout complexities caused by the use of carrier structures and thick silicon regions.
Innovation Solution
The semiconductor device incorporates a silicon-on-insulator architecture with a first silicon region of reduced thickness and a second silicon region of greater thickness, eliminating the offset between transistor and memory device regions, and using a carrier structure to facilitate the formation of buried digit lines and reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a carrier structure with thick silicon region is used to form buried digit lines, then the formation of buried digit lines is facilitated, but the device size and layout complexity increase due to offset between transistor and memory device regions
Solution Approach 1:
The patent divides the silicon structure into two distinct regions: a first silicon region with reduced thickness for the transistor device region, and a second silicon region with greater thickness for the memory device region. This segmentation allows each region to be optimized independently, enabling buried digit line formation in the thicker second silicon region without increasing the overall device footprint, as the thinner first silicon region maintains compact transistor dimensions.
Solution Approach 2:
The patent applies local quality by providing different silicon thicknesses in different spatial locations: the first silicon region has reduced thickness optimized for transistor operations, while the second silicon region has greater thickness optimized for forming buried digit lines. This localized differentiation eliminates the need for offset between regions, reducing overall device size while maintaining ease of buried digit line formation where needed.
2Manufacturing precision
If advanced photolithography tools are used to reduce device size, then manufacturing precision improves, but layout complexities increase due to offset between device regions
Solution Approach 1:
By segmenting the silicon structure into two thickness regions, the patent eliminates the offset problem that would otherwise require complex layout adjustments. The segmented structure allows advanced photolithography tools to work with a unified, offset-free layout, simplifying the manufacturing process while achieving high precision in device size reduction.
Solution Approach 2:
The patent changes the thickness parameter of the silicon structure locally to eliminate offset between regions. This parameter change enables a simplified layout that is compatible with advanced photolithography tools, reducing layout complexity while maintaining the precision needed for small device dimensions.
3Ease of manufacture
If uniform thick silicon structure is used, then buried digit lines can be formed easily, but transistor device performance deteriorates due to excessive thickness
Solution Approach 1:
The patent segments the silicon structure into a first silicon region with reduced thickness for transistors and a second silicon region with greater thickness for buried digit lines. This segmentation allows the transistor region to maintain optimal thin thickness for high performance while the memory region provides the thickness needed for easy buried digit line formation, resolving the contradiction between manufacturing ease and device reliability.
Solution Approach 2:
The patent applies local quality by providing reduced thickness in the transistor device region to ensure high performance and reliability, while providing greater thickness in the memory device region to facilitate easy formation of buried digit lines. This localized differentiation allows each region to have the optimal thickness for its specific function without compromising the other.
Data Source
AI summary
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor device includes a carrier structure and a semiconductor structure. The semiconductor structure includes a silicon region having a first surface facing the carrier structure and a second, opposite surface facing away from the carrier structure. The semiconductor structure includes a gate structure on the first surface facing the carrier structure and an insulator region, where the insulator region is on the second, opposite surface facing away from the carrier structure.