SOI Wafer MEMS-IC Fabrication Using Imprint Lithography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity and cost associated with forming MEMS devices and ICs on a single wafer using high temperature oxidation and deposition processes, particularly in creating fine gaps and detailed mechanical features, necessitate a more efficient fabrication method.
Innovation Solution
A fabrication method utilizing standard foundry IC processing techniques on a silicon-on-insulator (SOI) wafer, incorporating imprint lithography for precise etching to create combined MEMS devices and ICs, allowing for the formation of fine gaps and detailed mechanical features, such as disk resonators, which can be used in RF applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high temperature oxidation and deposition processes are used to form MEMS devices and ICs on a single wafer, then electronic components can be integrated with MEMS structures, but the fabrication complexity and cost increase significantly
Solution Approach 1:
The fabrication process is segmented into distinct stages: first forming the MEMS mechanical structures using standard CMOS compatible processes, then adding electronic components in subsequent processing steps. This segmentation allows each subsystem to be optimized independently while maintaining overall integration on a single wafer.
Solution Approach 2:
The patent employs universal CMOS fabrication processes that can serve dual purposes: first creating the MEMS mechanical structures, then forming the electronic components. The same deposition and etching tools used for standard IC fabrication are utilized for MEMS structure formation, reducing the need for specialized equipment and processes.
2Ease of manufacture
If high temperature oxidation and deposition are used to create MEMS devices on a wafer, then mechanical elements can be formed, but the fabrication cost increases
Solution Approach 1:
The MEMS structures are formed using self-aligned processes where the mechanical elements are created as part of the standard CMOS fabrication sequence. The same layer deposits and etch steps that define transistor gates and interconnects also create the MEMS release holes and mechanical structures, eliminating the need for separate dedicated MEMS fabrication steps.
3Manufacturing precision
If standard foundry IC processing is used to create fine gaps in MEMS devices, then manufacturing precision can be achieved, but the ability to create detailed mechanical features is limited
Solution Approach 1:
The patent incorporates preliminary formation of release holes and mechanical feature definitions during the early CMOS processing steps, before the final interconnect layers are deposited. This preliminary action establishes the mechanical feature geometry early in the process when precise control is most critical, allowing subsequent steps to focus on electronic component integration without compromising mechanical feature quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the cost-effective construction of combined MEMS devices and ICs with precise mechanical features, facilitating the creation of RF filters and other electronic circuits, replacing surface acoustic wave filters in certain RF applications.
Implementation Method 1
standard foundry IC processing etching techniques may be used to etch away parts of the insulating layer and device layer of the SOI wafer to create fine gaps and other detailed mechanical features
Implementation Method 2
Deposition layers are added to the SOI wafer and etched away to form interconnects for electronic components
Data Source
AI summary
The present invention includes a fabrication method to construct a combined MEMS device and IC on a silicon-on-insulator (SOI) wafer (MEMS-IC) using standard foundry IC processing techniques. The invention also includes the resulting MEMS-IC. Deposition layers are added to the SOI wafer and etched away to form interconnects for electronic components for the IC. In one embodiment of the present invention, standard foundry IC processing etching techniques may be used to etch away parts of the insulating layer and device layer of the SOI wafer to create fine gaps and other detailed mechanical features of the MEMS device. Finely detailed etching patterns may be added by using imprint lithography instead of using contact or optical lithography.