SOI MIS Transistor Substrate Bias Control via Capacitor Coupling
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high-speed operation and low leakage current while maintaining stable substrate potential, as lowering threshold voltage tends to increase sub-threshold leakage current, and existing methods either require complex circuitry or unstable substrate potential.
Innovation Solution
A semiconductor apparatus using a Silicon On Insulator (SOI) structure with insulating isolation regions, featuring a perfectly depleted or partially depleted MIS transistor and a capacitor connected to the gate electrode and impurity diffusion layer, which controls substrate bias voltage through capacitor coupling, stabilizing the substrate potential and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the threshold voltage of a MOS transistor is lowered to achieve high-speed operation, then the operation speed is improved, but the sub-threshold leakage current increases
Solution Approach 1:
The substrate potential is made dynamically adjustable rather than fixed. By applying different substrate bias voltages (Vbs) depending on the operational state (active vs. standby), the threshold voltage can be optimized for speed during active operation and increased to reduce leakage during standby, thus resolving the contradiction between speed and leakage current
Solution Approach 2:
The threshold voltage is controlled by changing the substrate bias voltage parameter. During active operation, a lower substrate bias maintains low threshold voltage for high speed. During standby, increasing the substrate bias voltage raises the threshold voltage, thereby suppressing sub-threshold leakage current while maintaining acceptable operation characteristics
2Object-generated harmful factors
If a substrate bias application circuit is added to control substrate potential and reduce leakage current, then the sub-threshold leakage current is reduced, but the device complexity increases
Solution Approach 1:
The substrate bias voltage control is integrated into the existing transistor structure and control logic. The same control signals that drive the transistor operation also control the substrate bias, making the substrate potential adjustment a byproduct of normal operation control rather than requiring a separate dedicated bias application circuit
Solution Approach 2:
The substrate bias control is achieved using the transistor's own gate control mechanisms and existing circuit elements. The substrate potential is adjusted automatically based on the operational state without requiring external complex bias generation circuits, as the system uses its own operational signals to control the bias
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation and low power consumption during standby without requiring a substrate bias application circuit, maintaining stable substrate potential and reducing sub-threshold leakage current.
Implementation Method 1
a capacitor connected to a gate electrode and an impurity diffusion layer, controls substrate bias voltage through capacitor coupling
Implementation Method 2
a perfectly depleted or close to being perfectly depleted partially depleted-type MIS transistor formed on an electrically insulated silicon substrate
Data Source
AI summary
A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thin and substrate capacitance being reduced. The NchMOS transistor 1 is equipped with insulating isolation regions 5a, 5b that are perfectly depleted or partially depleted in a manner close to being perfectly depleted. An electrode 6 connected to a gate electrode G of the NchMOS transistor 1 and an impurity diffusion layer 7 are connected via a capacitor 2. A source electrode S is connected to a power supply terminal 3a, a gate electrode G is connected to an internal signal line S1, and a drain electrode D is connected to an internal signal line S2. Substrate bias voltage is then controlled using capacitor coupling when the NchMOS transistor 1 is turned on/off.