SOI MISFET Layout for Insulating Layer TDDB Reliability
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Solution Overview
Problem
The reliability of semiconductor devices using SOI substrates is compromised due to the degradation of the insulating layer's TDDB life when both gate and back gate potentials are applied, leading to increased voltage on the insulating layer and reduced insulation resistance.
Innovation Solution
The semiconductor device design includes separate regions for low and high withstand voltage MISFETs, with the high withstand voltage MISFETs formed in a bulk region without using back gate potential to avoid insulating layer degradation, and ion implantation energies are adjusted to minimize damage to the insulating layer, ensuring the reliability of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If both gate potential and back gate potential are applied to control MISFET operations, then the MISFET can achieve proper ON and OFF operations, but the voltage applied to the insulating layer increases and the TDDB life of the insulating layer is degraded
Solution Approach 1:
The semiconductor device is divided into a first region where both gate and back gate potentials are applied for proper MISFET operation, and a second region where only gate potential is applied to form a bulk region. This segmentation allows different operational modes in different regions, resolving the contradiction by isolating the high-voltage back gate operation to a specific area that does not compromise the insulating layer elsewhere.
Solution Approach 2:
The insulating layer thickness is made non-uniform, with a first insulating layer portion having a different thickness than a second insulating layer portion. The thinner portion is positioned in the bulk region where back gate potential is not applied, reducing the voltage stress on the insulating layer in that specific location and preserving TDDB life.
2Ease of operation
If back gate potential is applied to control high withstand voltage MISFET, then proper voltage control is achieved, but the reliability of the semiconductor device is lowered due to insulating layer degradation
Solution Approach 1:
The device structure is segmented into regions with different insulating layer thicknesses. The bulk region has a thinner insulating layer where back gate potential is not applied, allowing high withstand voltage operation without excessive voltage stress on the insulating layer, thus maintaining reliability.
Solution Approach 2:
The insulating layer thickness parameter is changed spatially across the device. By making the insulating layer thinner in the bulk region, the voltage density is reduced, allowing back gate potential control to be implemented without degrading the overall device reliability.
3Manufacturing precision
If ion implantation is performed to form impurity regions, then the MISFET characteristics are improved, but the insulating layer may be damaged
Solution Approach 1:
The insulating layer is made thinner in the bulk region where ion implantation is performed. This reduced thickness allows ions to be implanted more effectively to form the desired impurity regions while reducing the risk of damaging a thicker insulating layer, thus maintaining both manufacturing precision and insulating layer integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of the semiconductor device by extending the TDDB life of the insulating layer and maintaining low power consumption while suppressing leakage current and hot carrier-induced deterioration.
Implementation Method 1
a voltage applied to an insulating layer increases and the TDDB life of the insulating layer is likely to be degraded
Implementation Method 2
ion implantation energies are adjusted to minimize damage to the insulating layer
Data Source
AI summary
A low withstand voltage MISFET and a high withstand voltage MISFET are formed on an SOI substrate. An ON operation and an OFF operation of the low withstand voltage MISFET are controlled by a first gate potential to be supplied to a first gate electrode and a back gate potential to be supplied to a first well region. An ON operation and an OFF operation of the high withstand voltage MISFET are controlled by a second gate potential to be supplied to a second gate electrode in a state where a second well region is electrically floating. An absolute value of a second power supply potential to be supplied to a second impurity region is larger than an absolute value of a first power supply potential to be supplied to a first impurity region.