SOI Optical Modulator Capacitive Effect Reduction

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Solution Overview

Problem

Current electro-optic modulators face challenges in increasing data rates above 10 Gb/s, particularly in silicon-on-insulator modulators, with limited modulation rate, contrast, and high optical losses, as well as complexity and cost in integration and manufacturing.

Innovation Solution

The solution involves reducing access resistances and capacitive effects by modifying the structure of the semiconductor-on-insulator substrate, including increasing the thickness of doped areas connected to electrodes and modifying the substrate's resistivity and insulator layer thickness to minimize capacitive influence, while maintaining low optical losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the data rate is increased above 10 Gb/s in silicon-on-insulator modulators, then the modulation rate improves, but the capacitive effects of the structure and environment increase, limiting further performance improvement

Engineering Contradiction:
Improvemodulation rateVSAvoidcapacitive effects
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the semiconductor substrate material from beneath the doped areas, eliminating the source of parasitic capacitance. By taking out the substrate that causes the harmful capacitive coupling, the modulator can operate at higher data rates without being limited by these effects.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different structural qualities to different regions: the doped areas are left with reduced or removed substrate beneath them to minimize capacitance, while other regions maintain the full substrate structure. This local modification optimizes the electrical characteristics where needed without compromising the overall device structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If the access resistance is reduced to improve modulation performance, then the modulation contrast improves, but the structure becomes more complex requiring modified substrate removal processes

Engineering Contradiction:
Improvemodulation contrastVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the substrate removal process by selectively removing substrate material only from specific regions beneath the doped areas, rather than removing the entire substrate. This segmented approach reduces access resistance where needed while maintaining structural integrity elsewhere, avoiding unnecessary complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies substrate removal only to specific local regions beneath the doped areas rather than uniformly across the entire device. This localized modification simplifies the overall structure by maintaining the substrate where it is not needed, while achieving the electrical performance benefits where required.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If the insulator layer thickness is increased to reduce capacitive coupling, then the capacitive effect decreases, but the optical losses increase

Engineering Contradiction:
Improvecapacitive couplingVSAvoidoptical losses
Core Design Contradiction:
Object-affected harmful factorsVSLoss of energy

Solution Approach 1:

Instead of increasing the insulator layer thickness to reduce capacitance, the patent extracts and removes the substrate material entirely from beneath the doped areas. This elimination of the capacitive source is more effective than thickening the insulator and does not introduce the optical losses associated with increased insulator thickness.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the fundamental parameter from insulator thickness to substrate presence/absence. By transitioning from modifying the insulator layer to removing the substrate entirely, the solution achieves better capacitance reduction without the trade-off of increased optical losses.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables data rates above 10 Gb/s with improved modulation contrast and reduced optical losses, achieving a contrast of at least 5 dB at 40 Gb/s, compared to previous modulators which had limited performance at similar rates.

Implementation Method 1

the electro-optic modulator is an element that allows data to be transferred from an electrical signal to an optical wave

Methodology Applied
Scientific EffectElectro-optic effect: Electro-Optic Effects

Implementation Method 2

the optical modulation is generally produced by varying the density of carriers (electrons and/or holes) inside the optical waveguide. This variation in carrier density creates a variation in the refractive index, and therefore a variation in the phase of the guided optical wave

Methodology Applied
Scientific EffectCarrier density variation:

Implementation Method 3

the influence of the capacitive effect of the environment is reduced by modifying the structure of the substrate(s) plumb with the active region

Methodology Applied
Scientific EffectCapacitive coupling reduction: Capacitance

Data Source

PatentUS8693811B2High data-rate SOI optical modulator including a modified structure for reducing the capacitive effect between doped areas and a substrate
Publication Date: 2014.04.08 UNIV PARIS SACLAY
  • US8693811B2 patent drawing
  • US8693811B2 patent drawing
  • US8693811B2 patent drawing

AI summary

An electro-optic modulation component is provided, in particular on an SOI (semiconductor-on-insulator) substrate, improved for better performance at data rates above 10 Gb/s. This improvement is obtained by reducing the influence of the capacitive effects of the structure and of its environment, and more particularly in which the influence of the capacitance of the structure itself is limited by reducing the access resistance in the doped regions or the influence of the capacitive effect of the environment is reduced by modifying the structure of the substrate vertically beneath the active region, for example by thinning the silicon substrate or the insulator, or a combination of these features. The invention furthermore relates to a process for fabricating such a component and to a device or system that includes such a component. These improvements are applicable in 3D integration assembly processes and to electronic and optical hybrid circuits.