SOI MOS Capacitor Structure for Higher Breakdown Voltage
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Solution Overview
Problem
Integrated circuit (IC) devices face challenges in maintaining adequate dielectric thickness to avoid breakdown as device dimensions decrease, requiring a solution that increases breakdown voltage without increasing device size or process complexity.
Innovation Solution
The integration of a semiconductor-on-insulator (SOI) substrate with a buried insulator layer and a gate dielectric layer, along with n-type and p-type metal-oxide semiconductor capacitors, where the gate is electrically connected only to the n-MOS and p-MOS capacitors, allowing for increased breakdown voltage without significant dielectric thickness increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric thickness is increased to increase breakdown voltage (Vmax), then device reliability is improved, but device size increases
Solution Approach 1:
The patent divides a single thick dielectric layer into multiple thinner dielectric layers separated by conductive plates, creating a multi-stage capacitor structure. This segmentation allows the total breakdown voltage to be distributed across multiple layers, achieving high Vmax while maintaining compact device dimensions.
Solution Approach 2:
The patent transitions from a planar capacitor design to a three-dimensional stacked capacitor structure by adding vertical layers of dielectric and conductive plates. This dimensional change increases the effective capacitance and breakdown voltage without proportionally increasing the device footprint area.
2Volume of moving object
If dielectric thickness is decreased to reduce device size, then device size is reduced, but breakdown voltage decreases
Solution Approach 1:
By segmenting the dielectric into multiple thin layers with conductive plates in between, the patent achieves high total breakdown voltage through series connection of multiple dielectric layers, each at a safe thickness, while maintaining overall compact device size.
Solution Approach 2:
The patent creates a composite capacitor structure alternating between dielectric materials and conductive materials, forming a layered composite that provides both electrical insulation and conductivity in different layers, enabling high breakdown voltage in a compact configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables IC devices to function at higher voltages with minimal process changes, enhancing performance and reliability while maintaining or reducing dielectric thickness, thus addressing the challenge of maintaining adequate breakdown voltage.
Implementation Method 1
a gate dielectric layer over the SOI layer; an n-type metal-oxide semiconductor (n-MOS) capacitor, including: an n-well under the buried insulator layer
Implementation Method 2
an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate; and a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and including: a p-well adjacent the n-well
Data Source
AI summary
An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.