Bulk Resistance Control in SOI MOS Transistors
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Solution Overview
Problem
Traditional ESD solutions for SOI technologies face challenges in controlling bulk resistance, leading to reduced failure current and heat dissipation due to isolated transistors, which limits the performance of MOS devices in integrated circuits.
Innovation Solution
The introduction of an interleaved finger layout with isolation gates and external impedance elements, such as poly gates or silicide blocks, to control bulk resistance by isolating the bulk connection from the source and drain, allowing for adjustable resistance and improved ESD properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bulk connection methods are used in SOI technology, then transistor isolation is achieved, but bulk resistance control is lost and failure current is reduced
Solution Approach 1:
The bulk connection is segmented into multiple regions: a first bulk connection region connected to the first conductivity type well, and a second bulk connection region connected to the second conductivity type well. These regions are spatially separated and independently controlled, allowing different bulk potentials in different areas of the device, thus resolving the contradiction between isolation and control.
Solution Approach 2:
Different bulk connection regions are provided with different doping concentrations and geometries to achieve local optimization. The first bulk connection region has specific doping characteristics for NMOS control, while the second bulk connection region has different characteristics for PMOS control, allowing each region to be optimized for its specific function.
2Reliability
If guard rings are added around MOS devices to create bulk connection, then bulk control is improved, but device area increases
Solution Approach 1:
The bulk connection regions are merged with the source and drain extensions rather than being separate guard rings around the device. The first bulk connection region is merged with the source/drain extension of the first conductivity type, and the second bulk connection region is merged with the source/drain extension of the second conductivity type, eliminating the need for additional guard ring structures.
Solution Approach 2:
The bulk connection regions serve multiple functions: they provide bulk potential control for ESD protection, act as extension regions for the source/drain structures, and provide doping profiles that enhance device performance. This multi-functionality reduces the need for separate structures and minimizes area overhead.
3Reliability
If avalanche multiplication is increased to improve ESD triggering, then ESD protection is enhanced, but heat generation increases and failure current decreases
Solution Approach 1:
The doping concentration in the bulk connection regions is optimized to achieve the right balance between avalanche multiplication and heat generation. By controlling the doping profile in the bulk connection regions, the electric field distribution is modified to enable effective ESD triggering while managing the thermal effects of avalanche multiplication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control of bulk resistance, enabling faster triggering during ESD events while maintaining normal operation, thereby improving the performance of MOS devices by reducing leakage and enhancing multifinger triggering.
Implementation Method 1
at least one isolation gate formed in at least one of the source, the drain and the gate regions
Implementation Method 2
Avalanche multiplication on the drain side of the MOS triggers the intrinsic parasitic bipolar device
Implementation Method 3
a bulk connection 108 is placed at the end of the gate 106. The gate 106 extension to the bulk connection 108 area is necessary to avoid isolating the bulk connection form the gate area
Data Source
AI summary
The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.