SOI Device MOS Capacitor Discharge Path
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Solution Overview
Problem
The reduction in thickness of the gate dielectric layer in MOS capacitors used as decoupling capacitors in integrated circuits leads to a decrease in their ability to withstand charge buildup, causing destructive discharges, which affects the yield and reliability of silicon on insulator (SOI) devices as device sizes shrink.
Innovation Solution
A method for fabricating SOI devices that includes forming an MOS capacitor with a gate electrode and an impurity-doped region in the monocrystalline silicon layer, and providing an electrical discharge path from the capacitor's plate to the silicon substrate to safely discharge built-up charge, thereby preventing destructive discharges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate dielectric layer thickness is reduced to shrink device sizes, then device integration density is improved, but the capacitor's ability to withstand charge buildup deteriorates, causing destructive discharges
Solution Approach 1:
The harmful charge buildup is extracted from the capacitor structure by providing a dedicated discharge path that routes accumulated charge away from the thin gate dielectric layer to a safe discharge location, preventing destructive discharge while maintaining the reduced device size
Solution Approach 2:
An intermediary discharge path is introduced between the capacitor plates and the substrate, consisting of a conductive element and resistive element that safely mediates the discharge of built-up charge, preventing direct destructive discharge through the thin gate dielectric layer
2Manufacturing precision
If plasma etching steps are used to etch interlayer dielectric materials, then manufacturing precision is improved, but charge buildup on the capacitor occurs, leading to destructive discharge
Solution Approach 1:
The charge buildup, which is a harmful byproduct of plasma etching, is converted into a manageable condition by providing a controlled discharge path that safely dissipates the accumulated charge, allowing the continued use of plasma etching processes for precise manufacturing
3Reliability
If decoupling capacitors are placed between voltage busses to avoid logic errors from voltage spikes, then circuit reliability is improved, but charge buildup occurs on the capacitors, causing destructive discharge
Solution Approach 1:
A discharge path is preliminarily established in the capacitor structure before charge buildup becomes problematic, enabling proactive dissipation of accumulated charge during plasma etching steps and normal operation, preventing destructive discharge while maintaining the capacitor's protective function
Data Source
AI summary
A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.