SOI MOS Transistor Gate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
MOS transistors on SOI structures face performance limitations due to increased parasitic capacitance, which affects switching speed and overall performance, particularly in PDSOI-type transistors.
Innovation Solution
The design includes a silicon layer with a gate region having a non-intentionally doped gate portion and a partial insulating trench under the gate portion, which reduces parasitic capacitance by increasing the insulator thickness between the gate and body regions, and a body contact region positioned laterally next to the gate portion, optimized for reduced doping and silicide layer coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate region is heavily doped to improve electrical contact and reduce resistance, then electrical conductivity is improved, but parasitic capacitance increases which degrades switching speed
Solution Approach 1:
The gate region is divided into two zones with different doping levels: a first portion (gate electrode area) that is heavily doped for low resistance electrical contact, and a second portion (gate region extending beyond source/drain) that is less heavily doped to minimize parasitic capacitance. This local differentiation allows each zone to be optimized for its specific function.
Solution Approach 2:
The gate region is segmented into functionally distinct portions: a heavily doped gate electrode portion for electrical conduction and a less heavily doped extension portion for capacitance reduction. This segmentation enables independent optimization of electrical conductivity and parasitic capacitance characteristics in different spatial zones.
2Speed
If the insulator thickness under the gate is increased to reduce parasitic capacitance, then switching speed is improved, but manufacturing complexity increases
Solution Approach 1:
The insulator layer thickness is varied locally: it is thicker in the region under the gate extension portion (second portion) to reduce parasitic capacitance, while maintaining standard thickness under the channel region. This localized thickness variation achieves capacitance reduction without uniformly complicating the manufacturing process across the entire device.
Data Source
AI summary
The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.