SOI P-Channel MOS Transistor Layout for Breakdown Stability
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Solution Overview
Problem
Conventional high voltage MOS transistors on SOI substrates face issues with unstable negative resistance regions in drain voltage-current characteristics and reduced off-state breakdown voltage, leading to heat generation and increased costs due to larger device area.
Innovation Solution
A high voltage MOS transistor with a planar layout where the source body region is wholly surrounded by the drain region, featuring a semicircular end portion of the body region with a larger diameter than the central straight portion, and a gate electrode that does not overlap with the source region at the end portions, reducing current flow and electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the device area is increased to improve breakdown voltage characteristics, then the reliability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent changes geometric parameters of the device structure, specifically the curvature radii of the body region end portions and the overlapping configuration of the gate electrode. By optimizing these parameters, the device achieves improved breakdown voltage characteristics without requiring a proportional increase in overall device area, thereby maintaining cost-effectiveness while enhancing reliability.
2Strength
If the curvature radius of the end portion of the body region is increased to improve off-state breakdown voltage, then the off-state breakdown voltage is improved, but the device area increases
Solution Approach 1:
The patent employs asymmetry by designing the body region with end portions that have different curvature characteristics from the central portion. The end portions are specifically shaped with larger curvature radii to improve off-state breakdown voltage, while the central portion maintains a different configuration optimized for on-state performance. This asymmetric design allows localized optimization without uniform area expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes on/off-state breakdown voltage characteristics without increasing the device area, eliminating negative resistance regions and heat generation, resulting in improved drain voltage-current characteristics and cost-effectiveness.
Implementation Method 1
The gate electrode 7 serves as a field plate, and an electric field increases in the surface of the P-type drift region 5 located below the end portion of the field plate 7
Implementation Method 2
when a reverse bias is applied between the P+-type source region 8 and the P+-type drain region 9, a depletion region expands in a PN junction between the N-type body region 4 and a P-type drift region 5
Data Source
AI summary
In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.