SOI MOSFET Back Gate Dummy Stacks Prevent Short Circuits
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Solution Overview
Problem
MOSFETs face challenges with short channel effects and threshold voltage adjustments due to scaling down, where high doping concentrations in the channel region degrade performance and can cause short circuits between the back gate and source/drain regions, especially in SOI MOSFETs with thin buried insulating layers.
Innovation Solution
A MOSFET design on an SOI wafer with a back gate and dummy gate stacks, where conductive vias are used to electrically connect the gate stack and dummy gate stacks to the source and drain regions, avoiding short circuits and allowing for adjustable threshold voltage through doping type and concentration changes in the back gate, while using the dummy gate stacks as hard masks during doping and silicidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the threshold voltage is increased by increasing doping concentration in the channel region, then short channel effects are suppressed, but carrier mobility drops and device performance degrades
Solution Approach 1:
A dummy gate stack is introduced as an intermediary structure between the source/drain regions and the back gate. This dummy gate stack acts as a mediator that prevents direct conductive paths while still allowing the back gate to influence the channel region through the buried insulating layer, thus suppressing short channel effects without requiring high channel doping that would harm carrier mobility
Solution Approach 2:
The gate structure is segmented into a real gate stack for controlling the channel and a dummy gate stack for preventing short circuits and providing back gate access. This segmentation allows the back gate to be electrically connected through the dummy gate stack without creating direct short circuits between source/drain regions, enabling threshold voltage adjustment without compromising carrier mobility
2Reliability
If high doping concentration is used in the back gate to suppress short channel effects in short gate length MOSFETs, then short channel effects are reduced, but threshold voltage becomes excessively high for long gate length MOSFETs
Solution Approach 1:
The back gate doping concentration is made dynamically adjustable rather than fixed. By controlling the doping type and concentration in the back gate, the threshold voltage can be tuned to suit different MOSFET gate lengths on the same chip, allowing the system to adapt to different device requirements
Solution Approach 2:
The doping parameters (type and concentration) of the back gate are changed to achieve different threshold voltages. This parameter adjustment allows long gate length MOSFETs to have lower threshold voltages while short gate length MOSFETs maintain high threshold voltages for short channel effects suppression
3Productivity
If the buried insulating layer thickness is reduced to about 5 nm-30 nm in SOI MOSFETs, then integration density is improved, but unintentional conductive paths form between the back gate and source/drain regions
Solution Approach 1:
The dummy gate stack serves as an intermediary barrier that prevents unintentional conductive paths between the back gate and source/drain regions. Even when the buried insulating layer is thin (5-30 nm), the dummy gate stack structure blocks direct electrical connection, maintaining reliability while allowing thin insulation for high integration density
Solution Approach 2:
The dummy gate stack is formed in advance during the gate stack formation process, creating a protective structure before source/drain doping and silicidation processes. This preliminary action prevents conductive path formation during subsequent manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively adjusts the threshold voltage of MOSFETs by controlling the back gate's doping, prevents short circuits between the back gate and source/drain regions, and maintains manufacturing cost efficiency by integrating dummy gate stacks without additional deposition and patterning processes.
Implementation Method 1
it is desirable that the threshold voltage is adjusted differently for the MOSFETs with different gate lengths
Implementation Method 2
a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively
Data Source
AI summary
The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.