SOI MOSFET Active Regions Using Stressed BOX Edge Relaxation
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Solution Overview
Problem
Existing methods for creating strained silicon on insulator (SOI) wafers result in high dislocation densities and defects, limiting the effectiveness of MOSFET performance due to the use of relaxed SiGe layers that require plastic deformation and generate misfit dislocations, and conventional SOI wafers lack a mechanism for inducing strain in the top silicon layer.
Innovation Solution
The method involves etching isolation trenches into a semiconductor on insulator substrate with a stressed buried insulator structure, allowing for edge relaxation of the buried stressor layer to induce strain in the surface semiconductor layer, which can be further enhanced by ion implantation, thereby creating strained active regions with reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If relaxed SiGe layers are used to create strained silicon, then strain can be induced in the top silicon layer, but high dislocation densities and defects are generated
Solution Approach 1:
A buried insulating layer is introduced as an intermediary between the SiGe stressor layer and the silicon channel layer. This mediator allows the SiGe layer to be relaxed (reducing dislocations) while still providing strain to the channel through the insulating layer, thus resolving the contradiction between strain quality and dislocation density
Solution Approach 2:
The structure is segmented into distinct layers: SiGe stressor layer, buried insulating layer, and silicon channel layer. This segmentation allows each layer to be optimized independently - the SiGe layer can be relaxed without directly contacting the channel, reducing dislocation propagation while maintaining strain benefit
2Ease of manufacture
If conventional SOI wafers are used, then manufacturing is simple, but no mechanism exists for inducing strain in the top silicon layer
Solution Approach 1:
The SiGe stressor layer and buried insulating layer are prepared in advance during wafer fabrication, creating a pre-strained SOI structure. This preliminary action embeds the strain induction mechanism directly into the wafer structure, maintaining ease of manufacture while enabling strain capability
Solution Approach 2:
The SOI wafer is transformed into a composite structure combining SiGe, insulating material, and silicon. This composite approach enables strain induction functionality while maintaining compatibility with conventional SOI manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves biaxial or uniaxial strain in the surface semiconductor layer, reducing defects and enhancing MOSFET performance while maintaining low cost and flexibility in manufacturing, suitable for both silicon and other semiconductor materials.
Implementation Method 1
etching isolation trenches into a semiconductor on insulator substrate with a stressed buried insulator structure, allowing for edge relaxation of the buried stressor layer to induce strain in the surface semiconductor layer
Implementation Method 2
which can be further enhanced by ion implantation, thereby creating strained active regions with reduced defects
Data Source
AI summary
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.