SOI High Breakdown Voltage MOSFET With Deep Well Segmentation
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Solution Overview
Problem
Conventional high breakdown voltage MOS transistors face a trade-off between achieving high breakdown voltage and low on-resistance, with optimization of the P-type drain offset region concentration leading to increased on-resistance and decreased breakdown voltage.
Innovation Solution
A high breakdown voltage semiconductor device is designed using an SOI substrate with a first conductive type deep well region formed under the drain offset region, where the concentration peak of the deep well region-forming impurity is located deeper than the concentration peak of the drain offset region-forming impurity, optimizing both regions' concentrations to enhance breakdown voltage while minimizing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the concentration of the P-type drain offset region is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage decreases
Solution Approach 1:
The invention divides the drain region into two separate regions: a P-type drain offset region and an N-type deep well region. This segmentation allows each region to have optimized impurity concentrations for their specific functions, with the P-type region controlling on-resistance and the N-type region controlling breakdown voltage, thereby resolving the trade-off between these two parameters.
Solution Approach 2:
The invention applies different impurity concentrations to different regions: the P-type drain offset region has a higher impurity concentration to reduce on-resistance, while the N-type deep well region has a lower impurity concentration to maintain high breakdown voltage. This local differentiation of properties allows simultaneous optimization of both parameters that were previously conflicting.
2Reliability
If the concentration of the P-type drain offset region is decreased to increase breakdown voltage, then the breakdown voltage increases, but the on-resistance increases
Solution Approach 1:
By segmenting the drain region into P-type offset and N-type deep well regions, the invention allows the P-type region to maintain high impurity concentration for low on-resistance while the N-type region maintains low impurity concentration for high breakdown voltage, eliminating the need to compromise either parameter.
Solution Approach 2:
The invention implements local quality optimization by assigning different impurity concentrations to different regions: high concentration in the P-type drain offset region for low on-resistance and low concentration in the N-type deep well region for high breakdown voltage, allowing both parameters to be optimized simultaneously.
3Reliability
If a thick gate oxide film is used to increase breakdown voltage, then the breakdown voltage increases, but the on-resistance increases and device area increases
Solution Approach 1:
The invention changes the impurity concentration parameters in the drain regions to achieve high breakdown voltage without requiring a thick gate oxide film. By optimizing the impurity concentrations in the P-type and N-type regions, the invention achieves high breakdown voltage with a standard-thickness gate oxide, thereby maintaining low on-resistance and small device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves breakdown voltage while suppressing the increase in on-resistance, reducing parasitic capacitance and preventing punch-through, thereby enhancing the transistor's performance and frequency characteristics.
Implementation Method 1
a concentration peak of a first conductive type impurity introduced for formation of the deep well region is located deeper than a concentration peak of a second conductive type impurity introduced for formation of the drain offset region
Data Source
AI summary
A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.