SOI MOSFET Well Structure for Mixed Doping and Low Leakage
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Solution Overview
Problem
Forming integrated chips (ICs) on semiconductor-on-insulator (SOI) substrates that simultaneously optimize for both fast switching and low leakage current MOSFETs is challenging due to regionally discontinuous well regions, leading to floating well regions that degrade performance and require significant area for body contacts or separate grouping of MOSFET types, limiting power and timing optimization.
Innovation Solution
The implementation of multiple doped regions beneath source/drain regions on an SOI substrate, where a first doped region with one doping type is regionally continuous and a second doped region with a different type extends beneath the first, allowing both types of MOSFETs to be arranged continuously, reducing floating wells and the need for body contacts, thus enhancing IC performance and power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If well regions are formed to support both fast switching and low leakage current MOSFETs, then MOSFET performance is improved, but the well regions become regionally discontinuous creating floating wells that degrade performance
Solution Approach 1:
The patent divides the well region formation into multiple doped regions with different doping types (first doped region and second doped region) to support different MOSFET types (fast switching and low leakage current) while maintaining overall regional continuity. This segmentation allows each MOSFET type to have optimized doping while preventing floating wells through continuous extension beyond gate electrodes.
2Reliability
If body contacts are added to eliminate floating wells, then floating well issues are resolved, but significant area is consumed reducing MOSFET density
Solution Approach 1:
The patent extracts the body contact function by having the continuously extending doped regions themselves serve as the body connection path. The doped regions extend beyond the gate electrodes to contact the insulating layer, eliminating the need for separate body contacts while maintaining electrical connection and preventing floating wells.
3Reliability
If MOSFET types are grouped separately to optimize performance, then each MOSFET type achieves optimal conditions, but area is consumed and power/timing optimization is limited
Solution Approach 1:
The patent merges both fast switching MOSFETs and low leakage current MOSFETs into a single continuous well region structure. The first and second doped regions are formed continuously across different gate electrode regions, allowing different MOSFET types to coexist in close proximity without requiring separate grouping, thereby saving area and enabling flexible power and timing optimization.
4Reliability
If doped regions are formed to extend beneath gate electrodes, then floating wells are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary doped region formation before gate electrode formation. The first and second doped regions are formed in the second semiconductor material layer before the gate electrodes are created, allowing the doped regions to naturally extend beneath the gate electrodes and provide continuous body connection without requiring complex post-processing or alignment adjustments.
Data Source
AI summary
In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.