SOI MTP Memory Cell With Direct Gate Coupling
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Solution Overview
Problem
Current non-volatile multi-time programmable (MTP) memory designs based on bulk silicon technology face limitations in device performance due to increased short-channel effects (SCE) as they scale, leading to diminishing improvements.
Innovation Solution
The use of an ultra-thin silicon-on-insulator (SOI) substrate with a thin buried oxide layer and a fully depleted SOI (FDSOI) substrate, incorporating a floating gate transistor and a control capacitor with a control gate directly coupled to the floating gate, along with a device well that underlaps both gates, enhances performance by improving capacitive coupling and reducing SCE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk silicon technology is used for MTP memory, then manufacturing compatibility is maintained, but short-channel effects increase and device performance deteriorates
Solution Approach 1:
The patent changes the substrate parameter from bulk silicon to ultra-thin SOI with a specific BOX thickness (5nm-20nm), transforming the physical state of the silicon substrate to eliminate short-channel effects while maintaining manufacturing compatibility through standard SOI processing techniques
Solution Approach 2:
The invention transitions from planar bulk silicon to three-dimensional ultra-thin SOI structure with vertical stacking of memory cell components, utilizing the vertical dimension to achieve better electrical isolation and reduced SCE while maintaining planar processing advantages
2Productivity
If continuous scaling of MTP memory is pursued, then device density increases, but short-channel effects increase and performance improvements diminish
Solution Approach 1:
The patent changes the fundamental substrate parameter to ultra-thin SOI with controlled BOX thickness, enabling continued scaling to 28nm and 22nm nodes while maintaining performance through the inherent electrical isolation properties of the thin oxide layer
3Reliability
If control gate is directly coupled to floating gate, then capacitive coupling ratio improves, but device complexity increases
Solution Approach 1:
The patent merges the control gate and floating gate into a directly coupled structure, eliminating intermediate coupling elements and achieving maximum capacitive coupling ratio through direct electrical connection while using the same gate stack formation process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved memory cell performance with enhanced capacitive coupling ratios and reduced short-channel effects, leading to more efficient programming, reading, and data retention without the limitations of junction breakdown voltage, while maintaining compatibility with advanced technology nodes like 28 nm and 22 nm.
Implementation Method 1
a control capacitor having a control gate disposed on the SOI substrate. The control gate is directly coupled to the floating gate
Implementation Method 2
improving performance by improving capacitive coupling and reducing SCE
Data Source
AI summary
Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.