SOI Floating-Gate MTP Memory for Compact Neuromorphic MAC
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Solution Overview
Problem
Current neuromorphic neural hardware designs, such as SRAM-based and comparator-based implementations, exhibit a large footprint and high power consumption, hindering efficient integration and energy efficiency in integrated circuits.
Innovation Solution
An embedded multi-time programmable (MTP) floating gate memory cell is developed using a semiconductor-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process, featuring a planar multi-gate structure with a pass-gate and memory-gate, which reduces the need for dual polysilicon layers and simplifies processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If SRAM-based or comparator-based designs are used for neuromorphic neural hardware, then activation functions can be implemented, but the footprint becomes large and power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameters by using floating gate memory cells with multi-time programmability instead of SRAM or comparator circuits. This allows the memory threshold voltage to be programmed to different levels, enabling activation functions to be implemented by selecting appropriate threshold voltages, thereby reducing footprint while maintaining functionality
Solution Approach 2:
The floating gate memory cell serves multiple functions: it acts as both storage and as an active element for implementing activation functions through its programmable threshold voltage. This multi-functionality eliminates the need for separate SRAM or comparator circuits, reducing the overall footprint
2Ease of operation
If SRAM-based or comparator-based designs are used for neuromorphic neural hardware, then activation functions can be implemented, but power consumption increases
Solution Approach 1:
The patent utilizes the threshold voltage parameter of floating gate memory cells as a programmable control parameter for activation functions. By programming different threshold voltages, various activation functions can be implemented without requiring continuous power supply for comparison operations, significantly reducing power consumption
Solution Approach 2:
The floating gate memory cell inherently provides the activation function capability through its programmable threshold voltage characteristic. The device serves itself by using its own memory property (threshold voltage) to perform the activation function, eliminating the need for external power-hungry comparator circuits
3Ease of manufacture
If dual polysilicon layers are used for embedded flash memory, then floating gate memory can be implemented, but processing complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and eliminates the dual polysilicon layer requirement from the floating gate memory implementation. By using a single polysilicon layer with appropriate tunnel oxide thickness and charge trapping mechanisms, the complex dual-polysilicon gate stack is removed while maintaining floating gate functionality
Solution Approach 2:
The patent uses composite material structures in the tunnel oxide region (including nitride and oxide layers) to achieve the desired charge trapping and retention characteristics without requiring dual polysilicon gates. This composite approach simplifies the overall gate structure while maintaining functionality
Data Source
AI summary
A multi-time programable (MTP) memory cell is described. The MTP memory cell includes a buried oxide (BOX) layer. The MTP memory cell also includes a semiconductor-on-insulator (SOI) layer on the BOX layer. The MTP memory cell further includes a planar multi-gate structure. The planar multi-gate structure includes a pass-gate on the SOI layer. The planar multi-gate structure also includes a memory-gate.