SOI Non-Volatile Memory Structures for Scalability and Endurance
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Solution Overview
Problem
Current non-volatile memory devices face challenges such as high chip space requirements, scalability issues, and program disturbance, necessitating improved scalability, increased program/erase speed, and enhanced endurance.
Innovation Solution
Integrated circuits with non-volatile memory structures are fabricated using a semiconductor-on-insulator (SOI) substrate, where the insulator and upper semiconductor layers are selectively removed, and additional semiconductor material is deposited, allowing for the formation of non-volatile memory devices over partially or fully depleted SOI layers, enabling forward and back-bias control for improved gate control and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional non-volatile memory devices are used, then memory functionality is provided, but chip space is excessive and scalability is poor
Solution Approach 1:
The patent transitions from planar memory cell structures to vertically stacked three-dimensional memory structures. Multiple memory cells are stacked along the vertical dimension, allowing more memory cells to be packed into the same chip area, thereby reducing chip space requirements while improving scalability.
Solution Approach 2:
The patent implements nested structures where control gates, charge storage layers, and tunnel insulators are stacked concentrically and vertically. Multiple memory cells are nested within each other in the vertical direction, enabling high-density memory integration that reduces the area per memory cell and improves scalability.
2Reliability
If conventional memory structures are used, then basic memory operations are supported, but program disturbance occurs and endurance is limited
Solution Approach 1:
The patent divides the memory structure into segmented word lines and bit lines, allowing selective addressing and operation of individual memory cells. This segmentation enables precise control during program and erase operations, preventing program disturbance to non-selected cells and improving overall reliability and endurance.
Solution Approach 2:
The patent implements local quality variations in the memory structure, including regions with different insulator thicknesses, doping concentrations, and material compositions. These local variations optimize performance for specific functions such as reducing program disturbance in certain regions while enhancing endurance in others.
3Ease of manufacture
If manufacturing processes are simplified, then cost and time are reduced, but manufacturing precision may be compromised
Solution Approach 1:
The patent employs preliminary actions in the fabrication process, such as forming sacrificial layers and placeholder structures that guide subsequent processing steps. These preliminary structures enable precise formation of complex three-dimensional memory features while using standard manufacturing techniques, thereby maintaining manufacturing precision without significantly increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in enhanced program and erase performance, increased endurance, and cost-effective, time-efficient fabrication of non-volatile memory structures with improved scalability and reduced program disturbance.
Implementation Method 1
removing the upper semiconductor layer and the insulator layer from the first and second regions
Implementation Method 2
additional semiconductor material is deposited
Implementation Method 3
The split gate non-volatile memory cell may be erased by Fowler-Nordheim tunneling
Data Source
AI summary
Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.