SOI NWELL Capacitor Layout for Contaminant Gettering
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Solution Overview
Problem
In the fabrication of integrated circuits on semiconductor-on-insulator (SOI) wafers, contaminants tend to deposit on the front-side of the SOI wafer, where active devices are formed, posing a risk to device integrity, particularly for capacitors with N-type well (NWELL) regions.
Innovation Solution
The implementation involves an SOI substrate with sacrificial N-type well (NWELL) rings that act as an attractive barrier between the active NWELL regions and adjacent white space regions, providing localized protection without requiring additional masks or die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If separate masks are used to create getter regions for contaminant collection, then contaminant migration to active devices is reduced, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent merges the getter region formation with the existing NWELL fabrication process by using the same implantation mask. The getter regions are created as P-type regions adjacent to NWELL regions during the same fabrication step, eliminating the need for separate masking operations while still providing contaminant collection functionality.
Solution Approach 2:
The implantation mask serves multiple functions: it defines both the active NWELL regions and the getter regions simultaneously. This multi-functional approach allows a single masking step to accomplish both device formation and contaminant protection, reducing overall process complexity.
2Object-affected harmful factors
If getter regions are created using additional masking steps, then contaminant collection is improved, but manufacturing time and process steps increase
Solution Approach 1:
The getter regions are formed in advance during the standard NWELL fabrication process, before contaminants are introduced into the system. By pre-positioning the P-type getter regions adjacent to NWELL regions, the structure is prepared to immediately attract and hold contaminants without requiring additional later steps.
Solution Approach 2:
The fabrication of getter regions is combined with the NWELL formation process by performing phosphorus implantation in the same masking step that creates the P-type regions. This consolidation reduces the total number of fabrication steps while ensuring getter regions are properly positioned before contamination occurs.
3Reliability
If sacrificial NWELL rings are placed between active devices and white space regions, then gate oxide integrity is improved, but die area is consumed
Solution Approach 1:
The patent applies local quality by creating P-type getter regions only in specific locations adjacent to NWELL regions, rather than uniformly across the entire die. The getter regions are positioned locally where contaminant migration is most likely to occur, providing protection only where needed and minimizing unnecessary area consumption.
Solution Approach 2:
Instead of creating complete sacrificial rings around all devices, the patent uses partial getter regions that extend only partially around the NWELL regions. This partial coverage provides sufficient contaminant protection while consuming less die area than full环形 structures would require.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the migration of contaminants to vulnerable NWELL regions, thereby enhancing the gate oxide integrity (GOI) of capacitors and other electronic devices, while maintaining existing fabrication processes.
Implementation Method 1
sacrificial N-type well (NWELL) rings that protect the NWELL regions of these vulnerable devices by forming an attractive barrier between the active NWELL regions and adjacent white space
Data Source
AI summary
An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.