SOI Substrate Optoelectronic Packaging with Interposer
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Solution Overview
Problem
Conventional techniques for photonics applications face limitations due to outdated lithography for CMOS integration, lack of integrated CMOS functions, and challenges in high-speed data communication and thermal management in optoelectronic devices.
Innovation Solution
The integration of optoelectronic and CMOS devices using silicon-on-insulator (SOI) semiconductor substrates, with a buried oxide layer and active silicon layer, along with a back-end-of-line structure, and the use of interposers with conductive through vias and wiring for electrical connections, and thermal vias for heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If co-fabrication of optoelectronic devices with CMOS integrated circuitry is used, then integration is achieved, but lithography generation limits speed performance below 25 Gbit/s
Solution Approach 1:
The system is divided into separate optoelectronic chip and CMOS chip that are independently fabricated using their respective optimal lithography processes, then integrated through an interposer substrate. This segmentation allows each component to be optimized separately for its specific function and speed requirements.
Solution Approach 2:
An interposer substrate is introduced as an intermediary component between the optoelectronic chip and CMOS chip. The interposer provides high-speed electrical interconnects (28 Gbit/s capability) that overcome the limitations of direct wire bonding, enabling high-speed data transmission while maintaining integration.
2Reliability
If dedicated silicon photonics chips with no integrated CMOS are used, then photonics performance is optimized, but lack of integrated CMOS functions prevents on-chip controls
Solution Approach 1:
The system separates photonics functions (on optoelectronic chip) from control functions (on CMOS chip), allowing each to be independently optimized. The interposer enables communication between the two segments, providing integrated control capability without compromising photonics performance.
Solution Approach 2:
The interposer substrate serves as a mediator that connects the optoelectronic chip with integrated CMOS control functions. It provides the necessary electrical interconnects and signal routing to enable on-chip controls while maintaining the performance advantages of dedicated silicon photonics.
3Ease of operation
If wire-bond connections are used for high-speed I/O data communications, then connections are established, but scaling above 25 Gbit/s is extremely difficult
Solution Approach 1:
The interposer substrate replaces traditional wire-bond connections with advanced electrical interconnect structures that support 28 Gbit/s data rates. The interposer's controlled impedance traces and optimized signal paths enable high-speed communication while maintaining ease of assembly through standardized packaging.
Solution Approach 2:
The system changes the interconnection parameters by transitioning from wire-bond technology to planar trace interconnects on the interposer substrate. This parameter change enables higher bandwidth and faster data rates while maintaining manufacturing simplicity through standard PCB fabrication techniques.
4Ease of operation
If wire bonds are used with optoelectronic chips having laser diodes, then electrical connections are provided, but no room remains to install heat sink
Solution Approach 1:
The interposer substrate provides additional vertical space and thermal pathways beneath the optoelectronic chip. Thermal vias and heat dissipation structures are implemented in the interposer and substrate layers, creating new dimensions for heat management that do not interfere with the optical path or electrical connections.
Solution Approach 2:
The interposer substrate acts as a thermal intermediary, providing dedicated thermal pathways and heat sink mounting surfaces separate from the electrical connection paths. This allows simultaneous optimization of electrical connectivity and thermal management without spatial conflict.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed data communication and effective thermal management, enhancing the performance and reliability of photonics devices by integrating CMOS functions and improving data transmission speeds beyond 25 Gbit/s while allowing for heat sink installation.
Implementation Method 1
An integrated optical waveguide structure is patterned from the active silicon layer of the integrated circuit chip
Implementation Method 2
The application board also includes a plurality of thermal vias formed therein in alignment with the integrated recess. The photonics package is disposed within the integrated recess of the application board such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias.
Data Source
AI summary
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.