SOI Substrate Vertical Insulating Pillars Air Gap
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Solution Overview
Problem
Conventional semiconductor-on-insulator (SOI) substrates face challenges in maintaining true SOI advantages and device performance at scaled dimensions below 45 nm due to silicon pillars overlapping with the semiconductor device layer, leading to alignment errors and process biases during fabrication.
Innovation Solution
The method involves forming a substrate with vertical insulating pillars that support the semiconductor device layer, creating an air gap between the base semiconductor substrate and the device layer, and filling this gap with an insulator material to form a buried insulator layer, allowing for a planar upper surface and improved structural support without the need for precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silicon pillars are used to support the semiconductor device layer in conventional SOI substrates, then structural support is provided, but alignment errors and process biases occur due to overlap between pillars and device layer
Solution Approach 1:
The patent removes the silicon pillars from the device region entirely, extracting the problematic overlapping structure. Instead, insulating pillars are placed only in isolation regions surrounding the device region, eliminating the source of alignment errors while maintaining necessary structural support through alternative means.
Solution Approach 2:
The patent segments the substrate into distinct device region and isolation regions, with insulating pillars confined to isolation regions only. This spatial segmentation prevents overlap between support structures and active devices, resolving the alignment precision issue.
2Ease of manufacture
If conventional fabrication processes are used for SOI substrates, then manufacturing is achieved, but device performance deteriorates at scaled dimensions below 45 nm due to alignment errors
Solution Approach 1:
The patent performs preliminary patterning to define isolation regions before forming insulating pillars. This preliminary action establishes precise boundaries that prevent subsequent alignment errors during pillar formation, ensuring device performance at scaled dimensions.
Solution Approach 2:
The patent introduces insulating material as an intermediary substance that provides structural support without the overlapping problems of silicon pillars. The insulating material acts as a mediator between the substrate and device layer, maintaining ease of manufacture while improving reliability.
3Strength
If silicon pillars extend through the buried insulator layer, then structural support is maintained, but true SOI advantages are undermined due to bulk-like behavior in overlap regions
Solution Approach 1:
The patent applies local quality by placing insulating pillars only in isolation regions rather than throughout the entire substrate. This localized approach maintains structural support where needed while preserving the true SOI characteristics in device regions, preventing bulk-like behavior.
Solution Approach 2:
The patent extracts silicon pillars from the device region entirely, removing the source of bulk-like behavior. Insulating pillars are retained only in isolation regions, preserving the thin-film SOI advantages in active device areas while maintaining structural support elsewhere.
Data Source
AI summary
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.