SOI Photodetector Pixel Layout for Low Cross-Talk Readout
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Solution Overview
Problem
BSI CMOS image sensors face limitations such as limited silicon surface area for transfer and readout transistors, high noise, high parasitic capacitance, low optical and electrical isolation, and high cross-talk due to full-depth FDTI and partial-depth BDTI structures.
Innovation Solution
A semiconductor-on-insulator (SOI) DoP image sensor with a full-depth BDTI structure that isolates photodetectors, employs reflective STI gratings for high NIR sensitivity, and uses JFET or full-depletion transistors for low noise and high gain, with readout transistors on a different level than transfer transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-depth FDTI and partial-depth BDTI structures are used in BSI CMOS image sensors, then photodetector isolation is improved, but cross-talk increases and manufacturing complexity increases
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trench isolation (STI) structures between adjacent photodetectors and deep trench isolation (DTI) structures extending deeper into the substrate. This segmented approach provides both optical isolation (reducing cross-talk) and electrical isolation while maintaining manufacturability through standardized fabrication processes.
2Reliability
If full-depth FDTI structure is used, then electrical isolation is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies different isolation depths and configurations at different locations: STI structures are used between adjacent photodetectors at shallower depths, while DTI structures extend deeper in specific regions. This localized differentiation provides optimal electrical isolation where needed while reducing overall device complexity and manufacturing difficulty compared to uniform full-depth isolation.
3Reliability
If silicon surface area is increased for transfer and readout transistors, then transistor performance is improved, but pixel area increases reducing sensor resolution
Solution Approach 1:
The patent moves readout transistors from the traditional planar layout to a vertical configuration using a raised active region or epitaxial layer. This dimensional transition allows transfer and readout transistors to be stacked above the photodetector plane, increasing their effective surface area for improved performance without expanding the horizontal pixel footprint, thereby maintaining high sensor resolution.
4Measurement precision
If noise and parasitic capacitance are reduced, then signal quality is improved, but device design complexity increases
Solution Approach 1:
The patent introduces intermediate isolation structures (shallow trench isolation) between photodetectors and transfer/readout transistors, and uses deep trench isolation to separate different device layers. These intermediary structures act as electrical barriers that reduce parasitic capacitance coupling between adjacent components, improving signal quality while using well-established isolation techniques that do not significantly increase device design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances scaling, reduces noise and parasitic capacitance, improves optical and electrical isolation, and increases full well capacity, leading to low cross-talk and high anti-blooming.
Implementation Method 1
employs reflective STI gratings for high NIR sensitivity
Data Source
AI summary
Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.