SOI Devices for Plasma Display Panel Driver Chips

Solution Overview

Problem

Conventional SOI devices for plasma display panel driver chips have limited vertical withstand voltage due to the thickness of the buried oxide layer, which affects the performance and cost of high-voltage devices, and the process complexity increases the manufacturing cost.

Innovation Solution

Incorporating n+ doped regions with higher doping concentrations at the interface between the n-type SOI layer and the buried oxide layer, which form a hole inversion layer and ionized N+ regions, enhancing the electric field in the buried oxide layer while weakening it in the SOI layer, allowing for a thinner buried oxide layer to achieve higher vertical withstand voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the buried oxide layer thickness is increased to improve vertical withstand voltage, then the withstand voltage increases, but the chip area and device complexity increase

Engineering Contradiction:

Improvevertical withstand voltageVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the doping concentration parameter by introducing n+ doped regions with higher doping concentrations at the interface between the n-type SOI layer and the buried oxide layer. This parameter change enables the buried oxide layer to achieve higher withstand voltage with reduced thickness, resolving the contradiction between reliability improvement and area increase.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by creating n+ doped regions specifically at the interface between the n-type SOI layer and the buried oxide layer, rather than uniformly doping the entire structure. This localized high-doping region enhances the vertical withstand voltage capability at the critical interface without requiring a thicker buried oxide layer throughout the entire device.

Inventive Principle:

Principle #3Local quality

2Reliability

If deep trench dielectric isolation is employed to isolate HV devices, then latch-up is avoided, but process complexity and manufacturing cost increase

Engineering Contradiction:

Improvelatch-up preventionVSAvoidprocess steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the doping concentration parameter by introducing n+ doped regions with higher doping concentrations at the interface between the n-type SOI layer and the buried oxide layer. This parameter change enables the buried oxide layer to achieve higher withstand voltage with reduced thickness, resolving the contradiction between reliability improvement and area increase.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by creating n+ doped regions specifically at the interface between the n-type SOI layer and the buried oxide layer, rather than uniformly doping the entire structure. This localized high-doping region enhances the vertical withstand voltage capability at the critical interface without requiring a thicker buried oxide layer throughout the entire device.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If the buried oxide layer thickness is reduced to decrease chip area, then the chip size decreases, but the vertical withstand voltage decreases

Engineering Contradiction:

Improvechip areaVSAvoidvertical withstand voltage

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the doping concentration parameter by introducing n+ doped regions with higher doping concentrations at the interface between the n-type SOI layer and the buried oxide layer. This parameter change enables the buried oxide layer to achieve higher withstand voltage with reduced thickness, resolving the contradiction between reliability improvement and area increase.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by creating n+ doped regions specifically at the interface between the n-type SOI layer and the buried oxide layer, rather than uniformly doping the entire structure. This localized high-doping region enhances the vertical withstand voltage capability at the critical interface without requiring a thicker buried oxide layer throughout the entire device.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution increases the vertical withstand voltage of the buried oxide layer per unit thickness, reduces the self-heating effect, and enhances the overall performance of the SOI devices, enabling their use in 50V–300V PDP driver chips with improved power efficiency.

Implementation Method 1

Incorporating n+ doped regions with higher doping concentrations at the interface between the n-type SOI layer and the buried oxide layer, which form a hole inversion layer and ionized N+ regions, enhancing the electric field in the buried oxide layer

Methodology Applied

Scientific EffectHole inversion layer formation: Electric Field

Data Source

PatentUS8704329B2SOI devices for plasma display panel driver chip

Publication Date: 2014.04.22 UNIV OF ELECTRONICS SCI & TECH OF CHINA

AI summary

SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer.