Polysilicon Ground for SOI VC Inspection
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Solution Overview
Problem
Current methods for grounding front-end-of-line (FEOL) structures, such as gate stacks and active regions, in silicon-on-insulator (SOI) substrates are inadequate for in-line voltage contrast (VC) inspection, as existing techniques are either costly, non-representative, or violate design rules, making it impossible to create effective VC test structures for SOI technology.
Innovation Solution
A structure and method involving a polysilicon ground that intersects and extends through the shallow trench isolation (STI) and buried oxide (BOX) layers to the bulk silicon substrate, allowing for grounding of silicon active regions and gate stacks, enabling VC inspection without requiring special wafers or large capacitors, and providing a ground path before contact dielectric formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon ground is extended through the STI and BOX layers to the bulk silicon substrate, then effective grounding of FEOL structures is achieved, but the process complexity increases
Solution Approach 1:
The polysilicon ground is formed and extended through the STI and BOX layers to the bulk silicon substrate before the contact dielectric is deposited. This preliminary grounding action ensures that the FEOL structures have a valid ground path available during VC inspection, eliminating the need for post-grounding steps and special wafer processing.
Solution Approach 2:
The grounding approach transitions from a planar ground connection to a three-dimensional path that extends vertically through multiple layers (STI isolation layer, BOX buried oxide layer) to reach the bulk silicon substrate. This vertical dimensionality allows grounding without violating horizontal design rules.
2Measurement precision
If VC test structures are created with grounded active regions, then inspection capability is improved, but area consumption increases due to large capacitors
Solution Approach 1:
The invention extracts and removes the large capacitor component from the VC test structure design. Instead of using large capacitors to create virtual ground paths, the solution directly connects the active region to the bulk silicon substrate through the polysilicon ground, eliminating the area-consuming capacitor while maintaining inspection capability.
3Reliability
If special short loop wafers are used for grounding, then grounding is achieved, but manufacturing cost increases
Solution Approach 1:
The polysilicon ground structure serves multiple functions: it provides grounding for VC test structures, maintains compatibility with standard production wafer processing, and enables inspection without requiring special short loop wafers. This multi-functionality eliminates the need for expensive special wafers while achieving reliable grounding.
4Reliability
If the ground path is established through the first metal level, then grounding is achieved, then the test structure is covered by contact dielectric, but VC inspection capability is lost
Solution Approach 1:
The ground path is established through the polysilicon ground extending to the bulk silicon substrate before the contact dielectric is deposited. This timing ensures that the ground path is already in place and functional during VC inspection, allowing inspection capability to be maintained while having a valid ground path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables in-line VC inspection of gate stacks and active regions on full flow wafers using standard processing, allowing for effective charge dissipation and reducing the risk of charge damage during FEOL processing, while minimizing area usage and avoiding design rule violations.
Implementation Method 1
a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate
Implementation Method 2
the SEM induces a charge on all electrically floating elements whereas any grounded elements remain at a zero potential. This potential difference is visible to the SEM
Data Source
AI summary
Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.