SOI Polysilicon Resistor Layout for SAR ADC Linearity
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Solution Overview
Problem
Conventional polysilicon resistors in voltage-divider networks for successive approximation register analog-to-digital converters (SAR ADCs) suffer from nonlinearity due to edge-accumulation effects caused by strong electric fields at high voltages, leading to significant integral nonlinearity in 16-bit converters, which are not suitable for industrial applications.
Innovation Solution
The polysilicon resistor design involves a silicon-on-insulator (SOI) process where the substrate is divided into isolated areas, with a polysilicon resistor layer formed in correspondence, eliminating the strong electric field and edge-accumulation effect by ensuring the potential of the substrate isolation areas closely follows that of the polysilicon resistor blocks, thereby improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If polysilicon resistors are used in voltage-divider networks of SAR ADCs, then the device complexity is reduced and manufacturing is simplified, but the linearity deteriorates due to edge accumulation effects caused by strong electric fields at high voltages
Solution Approach 1:
The polysilicon resistor is divided into multiple segments (first polysilicon resistor and second polysilicon resistor) connected in series. Each segment operates at a different voltage level, with the first segment handling the high-voltage portion and the second segment handling the low-voltage portion. This segmentation prevents the formation of strong electric fields across the entire resistor, thereby eliminating the edge accumulation effect and improving linearity while maintaining the simplicity of polysilicon resistor manufacturing
Solution Approach 2:
Different portions of the voltage-divider network are assigned different resistance values and configurations based on their local voltage conditions. The first polysilicon resistor is designed with a resistance value adapted for high-voltage operation, while the second polysilicon resistor is optimized for low-voltage operation. This local optimization ensures that each segment operates within its optimal performance range, maintaining linearity across the entire voltage range from −10V to +10V
2Manufacturing precision
If metal thin film resistors are used to improve linearity, then the manufacturing precision improves, but the device complexity increases due to additional special process flow requirements
Solution Approach 1:
The patent replaces expensive and complex metal thin film resistors with polysilicon resistors, which are cheaper and can be manufactured using standard CMOS processes. By accepting the temporary limitation of polysilicon resistor linearity and compensating through clever circuit architecture (series connection with different resistance ratios), the solution achieves high linearity without requiring expensive metal thin film processes, thereby maintaining manufacturing simplicity while improving performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the integral nonlinearity of the SAR ADC, enhancing the accuracy and linearity of the successive approximation register analog-to-digital converter, meeting the demands of high-precision applications.
Implementation Method 1
The polysilicon resistor layer is isolated from the p-type substrate by an insulating silicon dioxide (SiO2) layer
Implementation Method 2
The electric field will cause carriers (electrons) within the polysilicon resistive layer to induce an edge-accumulation effect
Data Source
AI summary
The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter. A polysilicon resistor includes a first silicon substrate; a first silicon oxide layer disposed on the first silicon substrate; a second silicon substrate disposed on the first silicon oxide layer, wherein an insulating isolation structure extends through the second silicon substrate and divides the second silicon substrate into a plurality of substrate isolation areas separated from each other; a second silicon oxide layer disposed on the second silicon substrate; and a polysilicon resistor layer disposed on the second silicon oxide layer, wherein the polysilicon resistor layer includes a plurality of polysilicon resistor blocks separated from each other, the plurality of polysilicon resistor blocks is arranged in one-to-one correspondence with the plurality of substrate isolation areas, and the plurality of polysilicon resistor blocks are connected in series.