SOI Substrate Potential Stabilization via Through Via and External Electrode
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Solution Overview
Problem
The challenge in semiconductor devices with a silicon on insulator (SOI) substrate and a wafer level chip size package (W-CSP) through via structure is stabilizing the potential of the silicon substrate layer without increasing package size or altering the manufacturing process, as existing methods require modifications that complicate the manufacturing steps and package design.
Innovation Solution
A manufacturing method that forms a through via and a potential fixing external electrode on the SOI substrate, where the through via is electrically connected to an electrode pad and the potential fixing electrode is connected to the silicon substrate layer, allowing for potential stabilization without additional package size or manufacturing steps, using existing external terminals and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the W-CSP having the through via is applied to the SOI device, then the external terminal can be arranged at a desired position without being affected by the light receiving area, but the silicon substrate layer potential floats and causes circuit malfunction
Solution Approach 1:
A potential fixing external electrode is introduced as an intermediary element between the through via and the silicon substrate layer. This mediator provides a dedicated electrical connection path that stabilizes the substrate potential while preserving the flexible external terminal arrangement enabled by the through via structure.
2Reliability
If a substrate potential fixing electrode is formed at the upper surface of the SOI layer, then the silicon substrate layer potential can be fixed, but wire bonding is required and chip size increases
Solution Approach 1:
The potential fixing external electrode is merged with the existing external terminal structure formed through the via. By combining the potential fixing function with the existing via and terminal infrastructure, the solution eliminates the need for separate wire bonding operations and additional chip area while achieving substrate potential stabilization.
3Reliability
If the contact reaches the silicon substrate layer by etching the SOI substrate from the upper face side, then the substrate potential can be fixed, but the number of manufacturing steps increases
Solution Approach 1:
Instead of etching from the upper face side to reach the silicon substrate layer, the approach is inverted by utilizing the through via that already provides access to the substrate layer from the lower surface. This reversal of the etching direction allows the potential fixing electrode to be formed without additional complex etching steps.
Data Source
AI summary
A semiconductor device manufacturing method is disclosed. The method includes etching a silicon on insulator (SOI) from its surface (i.e., semiconductor substrate layer) to form a first trench and a second trench. The first trench extends through the SOI substrate and reaches an electrode pad. The second trench terminates in the semiconductor substrate layer. The manufacturing method also includes forming an insulation film that covers the surface of the semiconductor substrate layer as well as the side walls and bottoms of the first and second trenches. The manufacturing method also includes removing the insulation film from the bottoms of the first and second trenches to expose the electrode pad from the first trench bottom and to expose the semiconductor substrate layer from the second trench bottom.