SOI Power Amplifier Stacking for High Output Swing
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Solution Overview
Problem
Si-based power amplifiers face limitations due to the trade-off between transistor speed and breakdown voltage, resulting in low output power and efficiency, with existing designs struggling to stack more than four transistors without instability or requiring impractical components like diodes or transformers.
Innovation Solution
The use of silicon-on-insulator (SOI) technology to stack electrically isolated CMOS transistors with dynamic biasing networks, allowing for a larger number of transistors to be stacked without gate oxide breakdown, and securing the SOI substrate to an aluminum nitride substrate to reduce parasitic capacitances and enhance thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Si transistors are optimized for high speed RF and microwave applications, then transistor speed is improved, but breakdown voltage deteriorates (ranging from about 1.2V to several volts)
Solution Approach 1:
The patent divides the power amplifier into multiple stacked transistor stages (first power transistor stage, second power transistor stage, third power transistor stage) connected in series. Each transistor operates at a lower individual voltage, but the series combination achieves high total output voltage swing. This segmentation resolves the contradiction by allowing high-speed transistors to be used while achieving high breakdown voltage through series stacking.
2Power
If wide transistors are used to boost output power, then output power is improved, but device complexity increases (requiring parallel combinations and power-combining architectures)
Solution Approach 1:
The patent transitions from parallel transistor combinations (2D plane) to series stacking (3D vertical arrangement). Multiple transistors are stacked vertically in series, with each stage contributing to the total output voltage swing. This vertical dimensionality change achieves high output power without requiring complex parallel combining architectures, thereby reducing device complexity.
3Strength
If more than four transistors are stacked in series, then output swing voltage is improved, but stability deteriorates (gate oxide breakdown occurs)
Solution Approach 1:
The patent implements dynamic biasing circuits for each stacked transistor stage, allowing the bias voltages to adjust automatically during operation. This dynamic adjustment prevents any single transistor from experiencing excessive voltage stress that would cause gate oxide breakdown, thereby maintaining stability even with more than four stacked transistors. The dynamic biasing adapts to operating conditions to distribute voltage stress appropriately.
Solution Approach 2:
The patent incorporates feedback mechanisms in the biasing circuits of each transistor stage. The biasing is not fixed but responds to the actual operating conditions of the stacked transistors. This feedback control ensures that voltage distribution across the stack remains within safe limits, preventing gate oxide breakdown and maintaining circuit stability while enabling higher output swing voltages.
4Device complexity
If fixed gate-bias topologies are used, then device complexity is reduced, but efficiency deteriorates (low efficiency and precluding use in linear power amplifiers)
Solution Approach 1:
The patent replaces fixed gate-bias topologies with dynamic biasing circuits that adjust bias voltages based on operating conditions. Each transistor stage has its own dynamic biasing circuit that responds to signal amplitude and frequency variations. This dynamic approach improves power efficiency by optimizing the operating point of each transistor throughout the signal cycle, while the integrated design keeps the added complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases output swing voltage, reduces signal current, and improves efficiency by enabling the stacking of multiple transistors while maintaining stability, achieving high output power and efficiency in power amplifiers.
Implementation Method 1
securing the SOI substrate to an aluminum nitride substrate to reduce parasitic capacitances and enhance thermal conductivity
Data Source
AI summary
Illustrative embodiments of power amplifiers and associated methods are disclosed. In at least one embodiment, a method may include fabricating a power amplifier in a first silicon layer of a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises the first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first and second silicon layers; removing at least some of the second silicon layer from the SOI substrate, after fabricating the power amplifier; and securing the SOI substrate, after removing at least some of the second silicon layer, to an electrically non-conductive and thermally conductive substrate.