SOI Power Transistor with Tilted Implants for Drive Current
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Solution Overview
Problem
Medium voltage devices face challenges in drive current performance per unit area due to thicker gate oxides, with longer channel lengths contributing significantly to total resistance, making it difficult to reduce channel length in older technology nodes without angled tilted baseline implants.
Innovation Solution
The use of a silicon-on-insulator (SOI) substrate with a gate dielectric thickness of 20 nm to 60 nm and high-energy, large-angle tilted implants, combined with device layout engineering, to achieve a short channel length in medium voltage lateral power devices, even with relatively thick gate oxides, improving drive current and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker gate oxide is used in medium voltage devices, then breakdown voltage is improved, but drive current per unit area deteriorates
Solution Approach 1:
The patent changes the physical parameters of the device by reducing gate oxide thickness to 20-60nm and channel length to 50-500nm, enabling medium voltage operation with improved drive current. This parameter change allows the device to achieve both high breakdown voltage and high drive current per unit area, resolving the traditional trade-off between these two parameters.
2Reliability
If longer channel length is used, then voltage breakdown is improved, but total resistance increases and drive current deteriorates
Solution Approach 1:
The patent applies parameter changes by implementing channel lengths of 50-500nm, which is significantly shorter than traditional channels. Combined with drift engineering and RESURF technology, this enables the device to achieve both adequate voltage breakdown and low resistance, resolving the contradiction between voltage handling and current drive capability.
3Power
If channel length is reduced, then drive current is improved, but manufacturing difficulty increases due to thicker gate oxide and lack of angled tilted baseline implants
Solution Approach 1:
The patent changes the gate oxide thickness parameter to 20-60nm, which is thin enough to enable short channel fabrication using conventional manufacturing processes. This parameter change allows achieving 50-500nm channel lengths without requiring complex angled tilted baseline implants, thus improving drive current while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances drive current per unit area and reduces on-state resistance, achieving improved current drive capability and cell pitch, while maintaining a maximum rated voltage of 5V to 60V, outperforming submicron technology nodes with thinner gate oxides.
Implementation Method 1
a gate structure configured to control a channel within the body region, wherein each gate structure comprises a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm
Implementation Method 2
implanting a dopant species of a first impurity type into a surface of a silicon layer of a silicon-on-insulator (SOI) substrate to define a drift region; implanting a dopant species of a second impurity type opposite the first impurity type into the surface of the silicon layer and at an angle relative to the surface to define a body region
Implementation Method 3
after implanting the dopant species of the second impurity type, annealing the SOI substrate at a temperature of at least 900° C. for more than 1 minute
Data Source
AI summary
A semiconductor device includes a silicon-on-insulator (SOI) substrate and transistor cells electrically coupled in parallel to form a power transistor. Each transistor cell includes a source region in a silicon layer of the SOI substrate, a body region in the silicon layer and adjoining the source region, a gate structure configured to control a channel within the body region, a drain region in the silicon layer, and a drift region laterally separating the body region from the drain region. Each gate structure includes a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm. An effective length of the channel of each transistor cell is in a range of 50 nm to 500 nm. The power transistor has a maximum rated voltage in a range of 5V to 60V. Corresponding methods of producing the semiconductor device are also described.