SOI Wafer Pressure Sensor CMOS Compatibility
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Solution Overview
Problem
Existing pressure sensor manufacturing processes using SOI wafers are poorly compatible with standard CMOS manufacturing processes, requiring non-standard steps and being expensive, and struggle to achieve long-term accuracy due to residual gases in the sensor cavity.
Innovation Solution
A method involving two wafers where the second wafer, an SOI wafer, is mounted on top of the first wafer with integrated circuitry, forming a cavity that is evacuated and sealed after assembly, using a sealing layer to cover the seam between the wafers, allowing for standard CMOS or bipolar manufacturing processes and improving vacuum quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a recess is formed in the first wafer and covered by an SOI wafer with the handle substrate removed, then a deformable membrane is formed over the recess, but the design is poorly compatible with standard CMOS manufacturing processes and requires additional non-standard manufacturing steps that render it expensive
Solution Approach 1:
The invention divides the manufacturing process into distinct segments: forming the recess and initial structure in the first wafer using standard CMOS processes, then separately preparing and bonding the SOI wafer in subsequent steps. This segmentation allows each part to be manufactured using appropriate processes, maintaining CMOS compatibility while achieving the required membrane structure.
Solution Approach 2:
The invention performs preliminary actions by forming the recess, depositing material layers, and creating the cavity structure in the first wafer before bonding the SOI wafer. This preliminary preparation enables the use of standard CMOS processes for the initial structure, while the SOI wafer is prepared separately with its handle substrate already removed or thinned, avoiding the need to perform these complex operations during the main CMOS fabrication sequence.
2Device complexity
If the cavity is sealed immediately after formation, then the manufacturing process is simplified, but residual gases remain in the cavity compromising long term accuracy
Solution Approach 1:
The invention performs the cavity evacuation operation after the wafers are bonded together but before final sealing. An opening is temporarily maintained in the membrane to allow vacuum pumping to remove residual gases from the cavity. Only after evacuation is complete is the opening sealed, ensuring the cavity contains minimal residual gases for improved long-term accuracy while maintaining a relatively simple manufacturing sequence.
Solution Approach 2:
The invention introduces a temporary opening as an intermediary element that allows the cavity to be evacuated after sealing. This opening acts as a mediator between the sealed cavity environment and the external vacuum system, enabling residual gas removal without requiring the cavity to remain open during manufacturing. The opening is subsequently sealed to complete the hermetic seal with improved vacuum quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances compatibility with standard manufacturing processes, reduces costs, and achieves better long-term accuracy by removing residual gases and providing a cleaner cavity environment, suitable for both absolute and differential pressure sensors.
Implementation Method 1
The oxide layer of the SOI-wafer here acts as an ideal etch stop in the case where the substrate wafer is removed by dry or wet etching. This is due to high etch selectivity between silicon and oxide.
Implementation Method 2
The cavity is evacuated by forming an opening to the cavity and then sealing the cavity by closing the opening using LPCVD.
Data Source
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AI summary
A pressure sensor is manufactured by joining two wafers (1a, 14), the first wafer comprising CMOS circuitry (2) and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer (1a), which is covered by the silicon layer (17) of the second wafer (14) to form a cavity (18). Part or all of the substrate (15) of the second wafer (14) is removed to forming a membrane from the silicon layer (17). Alternatively, the cavity can be formed in the second wafer (14). The second wafer (14) is electrically connected to the circuitry (2) on the first wafer (1a). This design allows to use standard CMOS processes for integrating circuitry on the first wafer (1a).