Silicon-on-Insulator Fabrication via Recrystallization
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Solution Overview
Problem
The formation of integrated circuits using silicon-on-insulator wafers is costly, and methods to create buried silicon dioxide layers are problematic for controlling lateral and vertical dimensions, leading to stress and issues during photolithographic operations.
Innovation Solution
An integrated circuit is formed by creating an isolation recess in a silicon substrate, filling it with dielectric material, and using a non-selective epitaxial process to grow single-crystalline silicon on exposed areas and polycrystalline or amorphous silicon on buried isolation layers, followed by radiantly-induced recrystallization to achieve a single-crystalline semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-on-insulator wafers are used to form integrated circuits with dielectrically isolated silicon, then isolation performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon-on-insulator wafers with a cost-effective alternative using bulk silicon wafers and deposited dielectric layers. The isolation structure is created through standard semiconductor fabrication processes (oxidation, deposition, etching) rather than requiring specialized SOI wafers, significantly reducing material costs while maintaining isolation performance
Solution Approach 2:
The patent changes the fundamental approach from using pre-formed SOI wafers with specific physical parameters to creating isolation structures through controlled deposition and etching processes. This allows optimization of dielectric layer thickness and composition to achieve the required isolation performance at lower cost
2Reliability
If oxygen implantation is used to form buried silicon dioxide layers, then isolation is achieved, but lateral and vertical dimension control deteriorates
Solution Approach 1:
The patent replaces the oxygen implantation process (which relies on ion diffusion and is difficult to control precisely) with a physical vapor deposition or chemical vapor deposition process followed by selective etching. This substitution of the formation mechanism enables precise control over the lateral and vertical dimensions of the dielectric isolation layer through standard lithography and etching techniques
Solution Approach 2:
The patent forms the dielectric isolation layer through a controlled deposition process before final device formation, allowing precise definition of the isolation region boundaries through lithography and etching. This preliminary structuring enables accurate dimension control that cannot be achieved through post-formation implantation methods
3Reliability
If oxygen implantation is used to form buried silicon dioxide layers, then isolation is achieved, but stress on the wafer increases
Solution Approach 1:
The patent replaces the high-stress oxygen implantation process with a low-stress deposition and etching process. The dielectric material is deposited conformally and then selectively removed to form isolation regions, avoiding the mechanical stress and potential wafer damage associated with high-energy ion implantation
Solution Approach 2:
The patent converts the potential harm of high-stress implantation into a benefit by using a gentler deposition-based approach that inherently reduces stress while achieving the same isolation function. The process transforms a harmful high-stress method into a beneficial low-stress method that protects the wafer during fabrication
4Reliability
If thin layers of device quality silicon are formed over buried oxide layers, then device performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent prepares the substrate surface through controlled oxidation and selective etching before depositing thin silicon layers. This preliminary preparation creates a clean, well-defined surface that facilitates the formation of high-quality thin silicon layers with good crystalline structure, reducing manufacturing difficulty while maintaining device performance
Solution Approach 2:
The patent optimizes the thickness and composition of the dielectric isolation layer to enable subsequent formation of thin silicon device layers. By carefully controlling the isolation layer parameters, the process facilitates rather than hinders the formation of high-performance thin device layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces costs and stress, enabling precise control over layer dimensions and reducing defects, thus improving the efficiency and reliability of integrated circuit formation.
Implementation Method 1
a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer
Implementation Method 2
A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate
Data Source
AI summary
An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.