SOI Resistor Structure Using Thin Semiconductor Layer
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Solution Overview
Problem
Conventional methods for forming resistive structures in semiconductor devices require significant area consumption and process modifications to achieve high resistance values, limiting integration density and increasing costs.
Innovation Solution
Utilizing a very thin semiconductor layer, typically 15 nm or less, in SOI architectures to form resistive structures, which inherently provides high sheet resistance, and implementing a control mechanism to adjust the resistance value through electrode structures and ferroelectric materials, allowing for dynamic or static resistance tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form resistive structures with high resistance values, then the resistance value is improved, but the area consumption increases significantly
Solution Approach 1:
The patent changes the thickness parameter of the semiconductor layer to achieve high resistance values. By reducing the layer thickness to the nanometer scale (e.g., 10-100 nm), the sheet resistance increases dramatically, allowing high resistance values to be achieved within a compact area without requiring additional process steps
Solution Approach 2:
The patent transitions from planar resistance control to vertical dimension control by utilizing ultra-thin semiconductor layers. This dimensional change allows the resistance to be primarily determined by the thickness parameter rather than lateral dimensions, enabling compact resistor designs with high resistance values
2Manufacturing precision
If process modifications are made to achieve high resistance values, then the resistance value is improved, but the device complexity increases
Solution Approach 1:
The ultra-thin semiconductor layer serves multiple functions: it forms the resistive structure, maintains process compatibility with existing CMOS fabrication, and enables high resistance values without requiring additional lithography or implantation steps. The same thin-layer technology can be used for both resistors and other device components
Solution Approach 2:
The semiconductor layer inherently provides the desired high resistance property through its reduced thickness, eliminating the need for external process modifications. The material itself serves the resistance function without requiring additional doping, patterning, or treatment steps that would increase process complexity
3Ease of manufacture
If conventional resistive structures are used, then process compatibility is maintained, but the integration density decreases
Solution Approach 1:
By changing the thickness parameter to the nanometer scale, the patent achieves high resistance values that reduce the lateral footprint of resistors. This allows more resistors to be integrated per unit area, increasing integration density while maintaining compatibility with existing semiconductor manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-ohmic resistors with reduced area consumption and increased design flexibility, maintaining process compatibility while allowing for precise resistance adjustment, thus enhancing integration density and operational performance.
Implementation Method 1
a very thin semiconductor layer as a basic sheet material for forming resistive structures... the significantly reduced thickness of the basic semiconductor layer compared to conventional concepts... may result in a significantly increased sheet resistance
Implementation Method 2
a control mechanism so as to adjust the final resistance value of a resistive structure... by appropriately applying a control voltage across the semiconductor base layer of the resistive structure, which may sufficiently modify the overall conductivity of the semiconductor base layer
Data Source
AI summary
The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.