SOI RF Switch Harmonic Reduction via Induced Charge Drainage

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Solution Overview

Problem

Semiconductor RF switches on SOI substrates face significant secondary capacitive coupling due to high-frequency RF signals, leading to reduced effectiveness and harmonic generation, despite the use of buried insulator layers to minimize capacitive coupling.

Innovation Solution

The implementation of shallow trench isolation structures and doped semiconductor regions with opposite conductivity types, electrically grounded or forward-biased to drain electrical charges from the induced charge layer, reducing harmonic signals and enhancing RF switch performance by maintaining a constant capacitance and field shield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high frequency RF signals are used for radio frequency applications, then the RF signal frequency range is extended, but capacitive coupling between semiconductor devices increases linearly with frequency

Engineering Contradiction:

ImproveRF signal frequencyVSAvoidcapacitive coupling

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

An induced charge layer is formed in the bottom semiconductor layer to act as an intermediary that screens and reduces capacitive coupling between semiconductor devices in the top semiconductor layer, allowing high frequency RF signals to be used while mitigating the harmful capacitive coupling effect

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The capacitance value is dynamically changed by controlling the voltage applied to the induced charge layer, enabling the capacitance to be adjusted to minimize capacitive coupling at different RF signal frequencies

Inventive Principle:

Principle #35Parameter changes

2Power

If voltage is increased to 30V to drive RF signals, then RF signal power is improved, but capacitive coupling and harmonic generation increase

Engineering Contradiction:

ImproveRF signal powerVSAvoidharmonic generation

Core Design Contradiction:

PowerVSObject-generated harmful factors

Solution Approach 1:

The harmful capacitive coupling and harmonic generation caused by high voltage RF signals are converted into a beneficial effect by using the induced charge layer to screen and reduce these harmful effects, allowing high power RF signals to be transmitted while minimizing harmonic generation

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Object-affected harmful factors

If buried insulator layer is used to reduce parasitic coupling, then substrate coupling is reduced, but secondary capacitive coupling through the bottom semiconductor layer remains significant

Engineering Contradiction:

Improveparasitic couplingVSAvoidRF switch effectiveness

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The bottom semiconductor layer is segmented into regions with different capacitance values, allowing the induced charge layer to selectively reduce capacitive coupling in specific areas while maintaining other functions, thereby improving RF switch effectiveness

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces capacitive coupling and harmonic generation, improving the fidelity of RF signals and the overall performance of semiconductor RF switches by continually draining electrical charges from the induced charge layer.

Implementation Method 1

The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the SOI substrate reduces capacitive coupling between an individual semiconductor device and the substrate

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 3

the dielectric constant of silicon oxide, which isolates a top semiconductor layer containing devices from a handle substrate

Methodology Applied

Scientific EffectDielectric isolation: Dielectric

Data Source

PatentUS8026131B2SOI radio frequency switch for reducing high frequency harmonics

Publication Date: 2011.09.27 GLOBALFOUNDRIES US INC

AI summary

First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions, thereby reducing of harmonic signals in the semiconductor devices above and enhancing the performance of the semiconductor devices as a radio-frequency (RF) switch.