SOI RF Switch Resonator Circuit for Fast High-Power Switching
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Solution Overview
Problem
Traditional high power silicon on insulator (SOI) switches face challenges with large die area, substrate loss, parasitic substrate capacitance, and difficulty in achieving fast switching time without degrading insertion loss or obtaining low return loss due to large gate capacitance.
Innovation Solution
The implementation of a high power SOI switch using resonator circuits with LC resonators to reduce parasitic substrate capacitance, cascade resonators instead of series switches, and utilize internal and external DC blocking capacitors to enable fast switching times and improved power handling, integrated with CMOS technology for efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional high power switches use a large number of large sized stacked devices, then power handling capability is improved, but die area increases and substrate loss increases
Solution Approach 1:
The patent divides the traditional single large switch into multiple smaller switch devices connected in parallel. Each switch device handles a portion of the total power, allowing the system to achieve high power handling capability while using smaller individual devices that occupy less die area and generate less substrate loss.
2Power
If traditional high power switches use a large number of large sized stacked devices, then power handling capability is improved, but parasitic substrate capacitance increases
Solution Approach 1:
By segmenting the switch into multiple smaller parallel devices, the total parasitic substrate capacitance is distributed across fewer devices compared to using many stacked devices. This reduction in total parasitic capacitance improves switching performance while maintaining power handling capability.
3Speed
If fast switching time is achieved, then switching speed is improved, but gate capacitance increases
Solution Approach 1:
The patent uses multiple smaller switch devices in parallel instead of fewer large devices. The smaller gate areas of individual devices result in lower gate capacitance per device, and the parallel configuration maintains fast switching time while reducing total gate capacitance compared to traditional stacked configurations.
4Loss of energy
If insertion loss is reduced, then signal quality is improved, but return loss deteriorates
Solution Approach 1:
The patent applies different design optimizations to different parts of the switch circuit. By carefully designing the parallel switch configuration with appropriate device sizing and interconnection, the circuit achieves low insertion loss in the forward path while maintaining good return loss through localized impedance matching and optimized device geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced die area, improved switching times, low insertion loss, and enhanced power handling, addressing the limitations of traditional high power SOI switches by minimizing substrate capacitance and optimizing signal routing.
Implementation Method 1
The implementation of a high power SOI switch using resonator circuits with LC resonators to reduce parasitic substrate capacitance
Data Source
AI summary
An apparatus comprises a first RF port, a second RF port, a first resonator circuit and at least one second resonator circuit. The first resonator circuit and the second resonator circuit may be connected between the first RF port and the second RF port. The first resonator circuit may comprise a first inductor, a first capacitor, and a first stacked switch device. The second resonator circuit may comprise a second inductor, a second capacitor, and a second stacked switch device. The first capacitor and the first stacked switch device may be coupled in series across the first inductor. The second capacitor, the second inductor, and the second stacked switch device may be connected in parallel.