SOI RRAM Isolation Structure for Cross-Talk Noise Shielding
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Solution Overview
Problem
Resistive memory devices are susceptible to malfunction due to external noise sources like electromagnetic interference and voltage fluctuations, which compromises their reliability, especially when used in conjunction with high voltage devices or circuits.
Innovation Solution
The implementation of semiconductor structures with a buried insulating layer on a semiconductor-on-insulator substrate, combined with deep trench isolation and metallic moat structures, provides electrical shielding to suppress cross-talk noise, enhancing the noise immunity of resistive random access memory (RRAM) devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If resistive memory devices are used in conjunction with high voltage devices or circuits, then device functionality and integration are improved, but susceptibility to cross-talk noise and electromagnetic interference increases
Solution Approach 1:
The patent introduces deep trench isolation structures filled with conductive material (such as doped polysilicon or metal) as intermediary shielding elements between resistive memory devices and high voltage devices. These conductive trenches act as electromagnetic shields that intercept and redirect noise fields, preventing direct coupling between adjacent devices while maintaining physical integration on the same substrate.
Solution Approach 2:
The patent segments the semiconductor substrate into isolated regions using deep trench structures that physically divide the device layout. By creating discrete isolation zones filled with conductive material, the patent partitions electromagnetic fields into separate domains, preventing noise propagation from high voltage devices to resistive memory devices while allowing both to coexist on the same chip.
2Reliability
If deep trench isolation structures with conductive material are implemented, then noise immunity is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the isolation trench formation process with existing semiconductor manufacturing workflows by integrating deep trench etching and conductive material deposition into standard process sequences. The conductive fill material is deposited using established techniques such as chemical vapor deposition or electroplating, and the trench structures are formed using conventional deep reactive ion etching, thereby minimizing additional process complexity.
Solution Approach 2:
The deep trench isolation structures serve multiple functions simultaneously: they provide electrical isolation between devices, act as electromagnetic noise shields, and function as part of the overall device interconnect architecture. This multi-functionality reduces the need for separate dedicated shielding structures, thereby limiting the increase in device complexity while achieving improved noise immunity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the impact of external electromagnetic noise on RRAM devices, improving their reliability and operational stability, particularly in noisy environments such as those found in the automotive industry.
Implementation Method 1
The implementation of semiconductor structures with a buried insulating layer on a semiconductor-on-insulator substrate, combined with deep trench isolation and metallic moat structures, provides electrical shielding to suppress cross-talk noise
Data Source
AI summary
A semiconductor structure includes a semiconductor-on-insulator (SOI) substrate including a handle substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure that vertically extends through the top semiconductor layer and the buried insulating layer, and includes a first inner insulating liner laterally surrounding a first portion of the top semiconductor layer that is located in a first device region in a plan view, a first non-insulating moat structure laterally surrounding the first inner insulating liner, and a first outer insulating liner that laterally surrounds the first non-insulating moat structure; and a resistive memory array located on the first portion of the top semiconductor layer, and located entirely within the first device region in the plan view.


