SOI Schottky Barrier Transistors for Third-Order Distortion Control

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Solution Overview

Problem

Non-linearities in communication device circuitry cause harmonic and intermodulation distortion, particularly third-order intermodulation distortion, which is challenging to filter out due to its proximity to original frequencies, leading to interference issues in multichannel communication equipment.

Innovation Solution

A radio-frequency switch with integrated Schottky barrier contacts in the transistor's drain and source, implemented as a Silicon-on-Insulator (SOI) device, minimizes non-linearity effects by compensating for distortion, thereby reducing third-order distortion products.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional transistor switches are used in radio-frequency circuitry, then the device can operate across multiple communication bands and modes, but non-linearities cause harmonic and intermodulation distortion that is difficult to filter

Engineering Contradiction:
Improvemulti-band operation capabilityVSAvoidthird-order intermodulation distortion
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent integrates Schottky barrier diodes into the transistor structure to convert the harmful non-linear effects into beneficial compensation. The Schottky barriers generate distortion products that are equal in magnitude but opposite in phase to those generated by the transistor, thereby canceling out the third-order intermodulation distortion while preserving multi-band operation capability

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent creates a composite device by integrating Schottky barrier diodes with the transistor structure. This composite structure combines the switching functionality of the transistor with the non-linear compensation characteristics of the Schottky barriers, achieving both multi-band operation and reduced distortion

Inventive Principle:
Principle #40Composite materials

2Object-generated harmful factors

If Schottky barrier contacts are integrated into the transistor, then third-order distortion is reduced by 9 dBm, but the device complexity increases

Engineering Contradiction:
Improvethird-order intermodulation distortion powerVSAvoidtransistor structure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the Schottky barrier diode structure with the transistor by integrating the Schottky contacts directly into the source and drain regions. This consolidation eliminates the need for separate distortion compensation circuits, reducing overall device complexity while achieving 9 dBm reduction in third-order distortion power

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces third-order intermodulation distortion and harmonic distortion, improving signal isolation and linearity, as demonstrated by a 9 dBm reduction in third-order intermodulation distortion power, enhancing performance in wireless communication devices.

Implementation Method 1

A Schottky barrier contact (SBC) transistor includes a Schottky barrier contact integrated into a drain of the transistor and/or a Schottky barrier contact integrated into a source of the transistor

Methodology Applied
Scientific EffectSchottky effect:

Data Source

PatentUS11862725B2Transistors with schottky barriers
Publication Date: 2024.01.02 SKYWORKS SOLUTIONS INC
  • US11862725B2 patent drawing
  • US11862725B2 patent drawing
  • US11862725B2 patent drawing

AI summary

Circuits, systems, devices, and methods related to transistors with Schottky barriers are discussed herein. For example, a method of fabricating a transistor can include forming a p-well or an n-well in a substrate and forming a gate for the transistor. The method can also include doping a region within the p-well or n-well with a concentration below a threshold and forming a conductor layer on the doped region.