SOI SCR ESD Protection with Deep Trench Isolation
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Solution Overview
Problem
Conventional diode-string triggered SCR devices for electrostatic discharge (ESD) protection suffer from higher than ideal leakages due to the Darlington amplifier structure, which directs current through the substrate, leading to inefficiencies and increased capacitance.
Innovation Solution
The implementation of a silicon on insulator (SOI) substrate with deep trench isolation structures and shallow trench isolation regions to isolate diodes vertically and horizontally, preventing current leakage into the substrate and reducing capacitance, thereby enhancing the efficiency of ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a string of diodes with Darlington amplifier is used for ESD protection, then ESD protection capability is improved, but leakage current increases
Solution Approach 1:
The device is segmented into distinct functional regions using deep trench isolation structures that divide the substrate into isolated wells. Each diode in the string is contained within its own isolated well, preventing current leakage between adjacent structures and reducing overall leakage current while maintaining ESD protection capability.
Solution Approach 2:
Deep trench isolation structures filled with dielectric material serve as intermediary elements between adjacent diodes and substrate regions. These isolation structures act as barriers that block parasitic current paths, preventing the Darlington amplifier effect from causing excessive leakage while allowing the diode string to function for ESD protection.
2Reliability
If multiple diodes are strung together in a Darlington amplifier configuration, then ESD protection is enhanced, but current loss to substrate increases
Solution Approach 1:
Each diode in the multi-diode string is placed in a separately isolated well created by deep trench isolation structures. This segmentation prevents the cumulative current loss that occurs in conventional configurations where multiple diodes share common substrate paths, allowing enhanced ESD protection without proportional increase in substrate current loss.
Solution Approach 2:
The isolation characteristics are applied locally at each diode- substrate interface through deep trench isolation structures. This local isolation quality prevents current loss at each individual diode connection point to the substrate, and the effects compound across multiple diodes to significantly reduce total current loss while maintaining the multi-diode ESD protection structure.
3Reliability
If conventional diode-string SCR structure is used, then ESD protection is provided, but capacitance is high
Solution Approach 1:
The deep trench isolation structures segment the continuous substrate into isolated regions, reducing the effective area available for parasitic capacitance formation. By confining each diode to its own isolated well, the capacitance between adjacent structures is minimized, resulting in lower overall loading capacitance while maintaining the diode-string SCR ESD protection function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in approximately 36.5% lower loading capacitance and 2 to 3 times lower leakage levels compared to conventional diode triggered SCR devices, maintaining current efficiency across any number of diodes in a string without additional substrate leakage.
Implementation Method 1
The deep trench isolation structures provide vertical isolation between the each of the diodes in the string of diodes, and the buried dielectric layer provides horizontal isolation between the well of each diode and the lower silicon based substrate to prevent loss of current
Data Source
AI summary
A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.