SOI Substrate Fabrication Reducing SECCO Defects
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Solution Overview
Problem
Current methods for fabricating semiconductor on insulator (SOI) substrates fail to achieve SECCO defect densities below 100 defects per cm², especially for thin device layers, due to limitations in existing processes such as SmartCut™ and thermal treatment methods which introduce additional defects or require expensive high-temperature furnaces.
Innovation Solution
A method combining ion implantation with helium and hydrogen ions, followed by thermal treatments including rapid thermal annealing (RTA) and sacrificial oxidation steps, split into multiple thinning stages, to reduce SECCO defects by optimizing process parameters like temperature and atmosphere, achieving synergistic effects in defect reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard SmartCut process is used to transfer device layer, then device layer is transferred onto handle substrate, but SECCO defect density remains above 100 defects per cm²
Solution Approach 1:
The patent applies preliminary action by performing ion implantation (helium and hydrogen ions) and thermal treatments (rapid thermal annealing at 900-1100°C for 1-30 minutes) on the source substrate before the SmartCut transfer process. These preliminary treatments modify the crystal structure and reduce SECCO defects in advance, enabling the final transferred device layer to achieve defect densities below 100 defects per cm² while maintaining production throughput
Solution Approach 2:
The patent changes physical and chemical parameters of the source substrate through controlled thermal treatments at specific temperature ranges (900-1100°C) and durations (1-30 minutes), and through ion implantation with specific doses (1x10¹⁵ to 1x10¹⁷ ions/cm²). These parameter changes fundamentally alter the substrate properties to reduce SECCO defects, achieving defect densities below 100 defects per cm² without sacrificing manufacturing productivity
2Shape
If thermal treatment is applied to reduce surface roughness, then surface quality is improved, but additional defects such as slip lines are generated
Solution Approach 1:
The patent precisely controls thermal treatment parameters (temperature range 900-1100°C, duration 1-30 minutes, rapid thermal annealing) to achieve surface roughness reduction while avoiding the formation of slip lines. By optimizing these parameters, the patent finds a window where surface quality improves without generating harmful defects, resolving the contradiction between surface quality and defect generation
3Ease of manufacture
If high temperature anneal is used to minimize high frequency roughness, then chemical mechanical polishing is not needed, but expensive high temperature furnaces are required and contamination control becomes difficult
Solution Approach 1:
The patent replaces the mechanical chemical mechanical polishing process with a thermal treatment process (rapid thermal annealing at 900-1100°C for 1-30 minutes). This substitution eliminates the need for expensive polishing equipment and complex contamination control systems associated with high temperature furnaces, while achieving the same surface quality improvement. The thermal treatment is performed under controlled conditions that avoid the drawbacks of conventional high temperature processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves SECCO defect densities of less than 100 defects per cm², and in some cases below 50 defects per cm², even for device layers thinner than 1000Å, while maintaining a balance between throughput and defect reduction, suitable for applications in memory devices.
Implementation Method 1
providing a predetermined splitting area inside the source substrate, characterized by a modified material property in comparison to the rest of the source substrate
Implementation Method 2
a rapid thermal anneal of the silicon on insulator substrate with the device layer being protected by a layer of silicon oxide
Implementation Method 3
thin the device layer by at least 100 Å by oxidizing at least a portion of the device layer
Data Source
Figure 1
Figure 2a~2h
AI summary
The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate comprising the steps of: providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, attaching, preferably by bonding, the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle compound at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced SECCO defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3 x 106 atoms per cm2 and thinning comprises an oxidation step at a temperature of less than 925°C