SOI Structure Segmentation for Combined FD-SOI and RF-SOI
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Solution Overview
Problem
Existing semiconductor-on-insulator (SOI) structures face challenges in combining digital and radio frequency applications due to electrical losses in high resistivity substrates and issues with trapped charges, which hinder back-side polarization and junction leakage.
Innovation Solution
A multilayer semiconductor-on-insulator structure is designed with a high-resistivity substrate, charge-trapping layers, and insulation trenches to separate FD-SOI and RF-SOI regions, allowing for both digital and radio frequency components to be integrated effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high resistivity substrate is used to reduce electrical losses for RF applications, then RF performance is improved, but the substrate is not compatible with transistors whose threshold voltage can be controlled by back-bias gate
Solution Approach 1:
The structure is divided into distinct regions: an RF region with high resistivity substrate for low loss, and a digital region with standard substrate for back-bias control. The insulation trench physically separates these regions, allowing each to be optimized independently for its specific application requirements.
Solution Approach 2:
Different substrate resistivity characteristics are applied to different locations: high resistivity in the RF region to minimize electrical losses, and standard resistivity in the digital region to enable back-bias gate operation. This local differentiation resolves the contradiction by allowing both properties to coexist in their respective domains.
2Loss of energy
If a trap-rich layer is combined with high resistivity substrate to improve RF performance, then electrical losses are reduced, but back-side polarization is hindered and junction leakage problems occur
Solution Approach 1:
The trap-rich layer is completely removed from the structure. Instead of using a trap-rich layer to reduce electrical losses, the patent relies on the high resistivity substrate alone and uses insulation trenches for electrical isolation, thereby eliminating the harmful effects of trapped charges on back-side polarization and junction leakage.
Solution Approach 2:
The insulation trench acts as an intermediary element that provides electrical isolation between adjacent regions. This allows the high resistivity substrate to reduce electrical losses without requiring a trap-rich layer, while the trench prevents any potential interference or leakage between regions.
3Reliability
If dual BOX technology is used for digital applications, then electrostatic characteristics are improved, but the structure is not suitable for combining both RF and digital applications
Solution Approach 1:
The structure segments different application requirements into separate regions: digital components use the dual BOX configuration for improved electrostatic characteristics, while RF components use the high resistivity substrate configuration for reduced electrical losses. The insulation trench enables this functional segmentation within a single integrated structure.
Solution Approach 2:
The structure achieves multi-functionality by supporting both digital and RF applications within the same device. The first substrate region provides dual BOX for digital components, while the second substrate region provides high resistivity for RF components, allowing the structure to serve multiple purposes simultaneously.
Data Source
Figure 1~2
Figure 3A~3C
Figure 3D~4A
AI summary
The present invention relates to a multilayer semiconductor-on-insulator structure (1), comprising: - a stack, called rear stack, of the following layers from a rear face towards a front face of the structure: a semiconductor support substrate (2) whose electrical resistivity is between 00 Ω.cm and 30 kΩ·cm, a first electrically insulating layer (3), a first semiconductor layer (4), - at least one trench isolation (8) that extends in the rear stack at least into the first electrically insulating layer (3) and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure (1) being primarily characterized in that it furthermore comprises at least one FD-SOI first region and at least one RF-SOI second region.