SOI Structure with Selective Sub-Insulator Voids
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Solution Overview
Problem
Existing semiconductor-on-insulator (SOI) structures lack the ability to selectively adjust capacitance coupling between different regions of a semiconductor layer and the substrate, which is necessary for optimizing performance in various applications such as phase locked loops and other low or mixed frequency applications.
Innovation Solution
The introduction of sub-insulator layer voids selectively placed in the substrate allows for varying capacitance coupling by positioning them below specific regions of a semiconductor device, such as the source and drain diffusion regions but not the channel region of an SOI field effect transistor, thereby reducing capacitance coupling between these regions and the substrate compared to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a complete insulator layer is provided between the semiconductor layer and substrate, then capacitance coupling between the semiconductor layer and substrate is minimized, but the ability to allow strong capacitance coupling in specific regions is lost
Solution Approach 1:
The patent applies local quality by creating voids in the insulator layer at specific locations beneath certain device regions. This allows different areas of the semiconductor device to have different capacitance coupling characteristics to the substrate - regions above voids have reduced coupling while regions without voids maintain strong coupling, enabling both isolation and substrate utilization simultaneously
2Adaptability or versatility
If the insulator layer is removed to allow substrate coupling, then strong capacitance coupling is achieved, but parasitic capacitance increases in regions where isolation is desired
Solution Approach 1:
The patent selectively removes portions of the insulator layer to create voids only in regions where substrate coupling is desired. This local modification allows the device to achieve strong capacitance coupling with the substrate in specific areas (such as beneath the channel region) while maintaining isolation in other areas (such as beneath source and drain regions), thereby eliminating parasitic capacitance where it would be harmful
3Ease of manufacture
If a uniform insulator thickness is maintained, then manufacturing simplicity is preserved, but selective capacitance adjustment between different device regions is not achieved
Solution Approach 1:
The patent maintains a uniform insulator layer thickness overall but introduces localized voids at specific positions beneath certain device regions. This approach preserves the simplicity of forming a uniform insulator layer while achieving selective capacitance control - the voids are created through targeted removal processes rather than attempting to form insulator layers of different thicknesses across the device
Solution Approach 2:
The patent achieves selective capacitance control by extracting (removing) portions of the insulator layer to create voids. This extraction approach is simpler than attempting to deposit insulator material with varying thicknesses, as it involves selective removal rather than precise selective deposition, thereby maintaining manufacturing ease while achieving the desired capacitance variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables selective minimization of capacitance coupling where necessary, enhancing the performance and reliability of SOI devices by allowing for stronger coupling where beneficial, while maintaining isolation between certain device regions and the substrate.
Implementation Method 1
capacitance coupling between the first section and the substrate will be less than capacitance coupling between the second section and the substrate
Data Source
AI summary
Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.