SOI Selector Diodes for CMOS Compatible Memory
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Solution Overview
Problem
Existing cross-point memory architectures face challenges with selectors that are not compatible with CMOS fabrication processes, suffer from low drivability, small on/off ratio, poor endurance, and limited processing temperature budget.
Innovation Solution
The use of silicon-on-insulator (SOI) based selectors with diodes formed using selective silicon epitaxy, which are CMOS-compatible, have a high on/off ratio, better endurance, and a higher thermal budget, and are embedded in the SOI structure with dummy gates to control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional selectors are used in 1S1R structure, then compact cell size is achieved, but CMOS compatibility is lost and drivability deteriorates
Solution Approach 1:
The patent changes the material parameters and structural parameters of the selector to achieve CMOS compatibility. Specifically, it uses silicon-on-insulator (SOI) based selectors with diodes formed using selective silicon epitaxy, which are compatible with CMOS fabrication processes while maintaining compact cell size. The dummy gate structure further modifies the electrical parameters to improve drivability without increasing area.
2Area of moving object
If conventional selectors are used in 1S1R structure, then compact cell size is achieved, but on/off ratio and endurance deteriorate
Solution Approach 1:
The patent employs composite material structures in the SOI-based selector with diodes formed through selective silicon epitaxy. This composite approach combines different silicon layers with specific doping profiles to achieve high on/off ratio and improved endurance while maintaining the compact 1S1R cell architecture. The dummy gate further enhances the electrical characteristics by controlling carrier flow.
3Area of moving object
If conventional selectors are used in 1S1R structure, then compact cell size is achieved, but processing temperature budget is limited
Solution Approach 1:
The patent changes the thermal parameters of the selector structure by using SOI-based materials and selective silicon epitaxy, which offer a higher thermal budget compared to conventional selectors. The silicon-on-insulator structure and epitaxially grown diodes can withstand higher processing temperatures required for subsequent CMOS fabrication steps, enabling better integration while maintaining compact cell size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in compact, efficient, and reliable memory devices with improved performance, including a higher ON current and better self-rectifying characteristics, compatible with CMOS fabrication processes.
Implementation Method 1
a second raised structure including a first diode layer having a conductivity of a second polarity opposite to the first polarity
Implementation Method 2
Selectors may include a silicon-on-insulator (SOI) based selector with diodes formed using selective silicon epitaxy
Data Source
AI summary
According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.